TEXTに投稿されたコード一覧

TEXT

#-------------------------------------------------------------------------------辞書、デフォルトサーフェス切り替え関係
#ダークネスの格好のまま他の歌を歌うのもなあと思ったのお試しででマルチキャラクタ取り入れてみました。
#クリックメニュー内の「別の歌が聞きたい」から飛ぶようにしています。
#マルチキャラクタの仕組みについてはコチラで。
#マルチキャラクタ・多重人格 - 里々wiki【 http://soliton.sub.jp/satori/index.php?%A5%DE%A5%EB%A5%C1%A5%AD%A5%E3%A5%E9%A5%AF%A5%BF%A1%A6%C2%BF%BD%C5%BF%CD%B3%CA 】
*別の歌が聞きたい
:リクエストデスネ!
ドノウタガイイデスカ?

_デイトポップ
_ダークネス
_おまかせ

_やっぱりやめる

#別人格用のメモです。
#*テクノ
#:テクノデスネ!
#キガエテクルノデ、スコシマッテテクダサイ・・・
#$辞書フォルダ	tecno
#$サーフェス加算値0	100
#$サーフェス加算値1	100
#$デフォルトサーフェス0	100
#$デフォルトサーフェス1	110
#オワリマシタ!

*デイトポップ
:デイトポップデスネ!
キガエテクルノデ、スコシマッテイテクダサイ・・・
$辞書フォルダ	sumidagawa
$サーフェス加算値0	200
$サーフェス加算値1	200
$デフォルトサーフェス0	200
$デフォルトサーフェス1	210
オマタセシマシタ!

*ダークネス
:ダークネスデスネ!
キガエテクルノデ、スコシマッテイテクダサイ・・・
$辞書フォルダ	.
$サーフェス加算値0	0
$サーフェス加算値1	0
$デフォルトサーフェス0	0
$デフォルトサーフェス1	10
ジュンビカンリョウデス!

*おまかせ
>おまかせ(選曲)

@選曲
デイトポップ
ダークネス

*おまかせデイトポップ
:デハ、デイトポップハドウデショウ?
:良い曲なので貴方も気に入ると思いますよ。
:キガエテクルノデ、スコシマッテイテクダサイ・・・
$辞書フォルダ	sumidagawa
$サーフェス加算値0	200
$サーフェス加算値1	200
$デフォルトサーフェス0	200
$デフォルトサーフェス1	210
オマタセシマシタ!
:フフフ・・・濁流にご注意を。
:ジズサンヤメテクダサイー!

*おまかせダークネス
:デハ、ダークネスハイドウデショウ?
:正直なところこの曲じゃないと私が居る意味があまりないですね・・・
:ソンナコトナイデスヨ!
キイテクレルヒトガオオイト、ウタイガイガアリマス!
:フフフ・・・
:ALTタチハキガエテキマスノデ、スコシマッテテクダサイ・・・
$辞書フォルダ	.
$サーフェス加算値0	0
$サーフェス加算値1	0
$デフォルトサーフェス0	0
$デフォルトサーフェス1	10
:フフフ・・・終わりましたよ。

*やっぱりやめる
:ワカリマシタ。

TEXT StepMania5.0で任意のパラメータを呼び出す

function GetSMParameter(song,prm)
	local st=song:GetAllSteps();
	if #st<1 then
		return "";
	end;
	local t;
	t=st[1]:GetFilename();
	if not FILEMAN:DoesFileExist(t) then
		return "";
	end;
	local f=RageFileUtil.CreateRageFile();
	f:Open(t,1);
	local tmp={};
	local pl=string.lower(prm);
	while true do
		l=f:GetLine();
		local ll=string.lower(l);
		if string.find(ll,"#notes:.*") or f:AtEOF() then
			tmp[1]="";
			break;
		-- [ja] BOM考慮して .* を頭につける
		elseif string.find(ll,".*#"..pl..":.*") then
			tmp=split(":",l);
			if tmp[2]==";" then
				tmp[1]="";
			else
				tmp=split(";",tmp[2]);
			end;
			break;
		end;
	end;
	f:Close();
	return tmp[1];
end;

function Str2Color(prm)
	local c={"1.0","1.0","1.0","1.0"};
	c=split(",",prm);
	if #c<4 then
		c={"1.0","1.0","1.0","1.0"}
	end;
	return c;
end;

TEXT ModelSimのバグ? 解決編

for(int n=0;n<4;n++)begin
	fork
		begin
			$display("n=%0d",n);
		end
	join_none
	#0;
end

TEXT ModelSimのバグ?

for(int n=0;n<4;n++)begin
	fork
		begin
			$display("n=%0d",n);
		end
	join_none
end

TEXT codetterのテスト。

class uart_env extends ovm_env;
	// コントロール変数
	protected int unsigned baud = 2400;

	function new(string name="uart_env" ,ovm_component parent);
		super.new(name ,parent);
	endfunction
	`ovm_component_utils_begin(uart_env)
		`ovm_field_int(baud, OVM_ALL_ON|OVM_UNSIGNED)
	`ovm_component_utils_end

	// メンバ変数
	protected virtual interface uart_if intf;

	// コンポーネント
	uart_master_agent uart_tx;

	// build
	function void build;
		super.build;
		set_config_int   ("uart_tx.sequencer" ,"count" ,0);
		uart_tx = uart_master_agent::type_id::create("uart_tx", this);
	endfunction

	// インターフェース接続
	function void assign_vi(virtual interface uart_if intf);
		this.intf = intf;
		uart_tx.assign_vi(intf);
	endfunction
endclass

TEXT Verilogのtest

問:次の代入式の結果、左辺がいくつになるか答えなさい。

reg [15:0]  A;
A = 8'bz010;

  1.  0000000000000010
  2.  zzzzzzzzzzzzz010
  3.  1111111111111010

----------------------------------------------

ModelSimでやってみた。

module test();

 reg [15:0] A;

 initial begin
   A = 8'bz010;
 end

endmodule

…結果。
00000000zzzzz010

TEXT CORDIC in Verilog

//
/* Portlist
CORDIC_SC cordic
(.Clock(Clock),.Reset(Reset),.Start(),.Theta(),
	.SinOut(),.CosOut(),.Busy(),.End());
*/

module CORDIC_SC
#(
	////////////////////////////////////////////////////
	// Parameters
	parameter bw_theta = 9,
	parameter bw_out = 16
)
(
	////////////////////////////////////////////////////
	// Ports
	input Clock,Reset,Start,
	input [bw_theta-1:0] Theta,
	output reg [bw_out-1:0] CosOut,SinOut,
	output reg Busy,End
);
	localparam fxp = 4;						//小数点位置
	localparam convert_vector	= 19898;	//変換ベクトル
	localparam bw_tromaddr	= 4;
	localparam bw_tromq		= 13;

	////////////////////////////////////////////////////
	// Registers
	reg signed [bw_out:0] 		rX,rY;		//符号付
	reg [bw_theta-1:0]			rInTheta;	//入力Thetaを格納するだけ
	reg signed [bw_tromq+1:0]	rTheta;		//Thetaを計算した結果を格納する
	reg [bw_tromaddr-1:0]		rTROMAddr;	//Startを遅延させる
	reg rDStart;

	////////////////////////////////////////////////////
	// Net
	wire signed [bw_out:0] wResAsX,wResAsY;	//AddSubの結果を出力
	wire signed [bw_out:0] wSX,wSY;			//X,Yをシフトした数値
	assign wSX[bw_out] = wSX[bw_out-1];
	assign wSY[bw_out] = wSY[bw_out-1];

	wire signed [bw_tromq+1:0] wResAsTheta;
	wire [bw_tromq+1:0] wTROMQ;
	assign wTROMQ[bw_tromq+1:bw_tromq] = 2'b0;

	wire [fxp-1:0] wFxp = 1'b0<<fxp;
	wire signed [bw_tromq+2:0] wInTheta = {2'b0,rInTheta,wFxp};

	wire wSeqEn		= (rTROMAddr < bw_tromq) && Busy;
	wire wEnd		= Busy && !wSeqEn;

	////////////////////////////////////////////////////
	// Instantiations

	//Address Depth:13	Q BitWidth:13	4bit FixPoint
	DISTROM_CORDIC_THETA theta_rom (.Address(rTROMAddr), .OutClock(Clock),
    .OutClockEn(1'b1), .Reset(Reset), .Q(wTROMQ[bw_tromq-1:0]));

	//算術右シフトレジスタ
	wire wRSStart = rDStart | wRSEnd;
	SRightShifter2 #(.bw_in(bw_out)) rs2(
		.Clock(Clock),
		.Reset(Reset|Start),	//Startでリセット
		.Start(wRSStart),
		.IN1(wResAsX[bw_out:1]),
		.IN2(wResAsY[bw_out:1]),
		.Amount(rTROMAddr),
		.OUT1(wSX[bw_out-1:0]),
		.OUT2(wSY[bw_out-1:0]),
		.Busy(wRSBusy),
		.End(wRSEnd)
	);

	wire wCompRes	= rTheta > wInTheta;	//Thetaを比較計算したθが大きければ1
	AddSub #(.width(bw_out+1)) asX(
		.SubEn(~wCompRes),
		.A(rX),
		.B(wSY),
		.S({1'bz,wResAsX})
	);
	AddSub #(.width(bw_out+1)) asY(
		.SubEn(wCompRes),
		.A(rY),
		.B(wSX),
		.S({1'bz,wResAsY})
	);
	AddSub #(.width(bw_tromq+2)) asT(
		.SubEn(wCompRes),
		.A(rTheta),
		.B(wTROMQ),
		.S({1'bz,wResAsTheta})
	);

	always@(posedge Clock or posedge Reset) begin
		if(Reset)begin
			rX			<=	0;
			rY			<=	0;
			CosOut		<=	0;
			SinOut		<=	0;
			Busy		<=	0;
			End			<=	0;
			rTheta		<=	0;
			rInTheta	<= 0;
			rTROMAddr	<= 0;
			rDStart		<= 0;
		end else begin
			rDStart	<= Start;
			if(Start) begin
				rX			<= convert_vector;
				rY			<= convert_vector;
			end else if (wRSEnd) begin
				rX		<= wResAsX;
				rY		<= wResAsY;
			end

			if(Start) begin
				rTheta		<= wTROMQ;
			end else if (wRSEnd) begin
				rTheta		<= wResAsTheta;
			end

			if(Start) begin
				rInTheta	<= Theta;
				Busy		<= 1'b1;
			end else if (wEnd) begin
				CosOut		<= wResAsX[bw_out-1:0];
				SinOut		<= wResAsY[bw_out-1:0];
				Busy		<= 1'b0;
			end

			if((Busy || rDStart) && !wRSBusy)
				rTROMAddr	<= rTROMAddr + 1;
			else if (wEnd)
				rTROMAddr	<= 0;

			if(End)
				End	<= 1'b0;
			else if (wEnd)
				End	<= 1'b1;

		end
	end
endmodule 

/* Portlist
RightShifter2 rs2(.Clock(Clock),.Reset(Reset),.Start(),.IN1(),.IN2(),
	.Amount(),.OUT1(),.OUT2(),.Busy(),.End());
*/
//符号付
module SRightShifter2
#(
	parameter bw_in = 15
)
(
	input Clock,Reset,Start,
	input [bw_in-1:0] IN1,IN2,
	input [3:0]	Amount,

	output reg [bw_in-1:0] OUT1,OUT2,
	output reg Busy,End
);

	//シフトレジスタを使って任意桁の右ビットシフト
	reg [3:0] rCount,rAmount;
	reg [bw_in-1:0]	rSR1,rSR2;

	wire wSeqEn = (rCount < rAmount);

	always@(posedge Clock or posedge Reset) begin
		if(Reset)begin
			rCount		<= 0;
			rSR1		<= 0;
			rSR2		<= 0;
			End			<= 0;
			Busy		<= 0;
			rAmount		<= 0;
			OUT1		<= 0;
			OUT2		<= 0;
		end else begin
			if(Start) begin
				rSR1		<= IN1;
				rSR2		<= IN2;
				rCount		<= 0;
				rAmount		<= Amount;
			end else if(wSeqEn) begin
				rSR1	<= {rSR1[bw_in-1],rSR1[bw_in-1:1]};
				rSR2	<= {rSR2[bw_in-1],rSR2[bw_in-1:1]};
				rCount	<= rCount + 1;
			end else if (!wSeqEn && Busy) begin
				OUT1	<= rSR1;
				OUT2	<= rSR2;
			end

			if(Start)
				Busy	<= 1'b1;
			else if (!wSeqEn)
				Busy	<= 1'b0;

			if(End)
				End		<= 1'b0;
			else if (!wSeqEn && Busy)
				End		<= 1'b1;
		end
	end
endmodule 

TEXT jtag_logic.vhd

-------------------------------------------------------------------------------
-- Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM
-------------------------------------------------------------------------------
-- Copyright (C) 2005-2007 Kolja Waschk, ixo.de
-------------------------------------------------------------------------------
-- This code is part of usbjtag. usbjtag is free software; you can redistribute
-- it and/or modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation; either version 2 of the License,
-- or (at your option) any later version. usbjtag is distributed in the hope
-- that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.  You should have received a
-- copy of the GNU General Public License along with this program in the file
-- COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
-- St, Fifth Floor, Boston, MA  02110-1301  USA
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY jtag_logic IS
	PORT
	(
		CLK : IN STD_LOGIC;        -- external 24/25 MHz oscillator
		nRXF : IN STD_LOGIC;       -- FT245BM nRXF
		nTXE : IN STD_LOGIC;       -- FT245BM nTXE
		B_TDO  : IN STD_LOGIC;     -- JTAG input: TDO, AS/PS input: CONF_DONE
		B_ASDO : IN STD_LOGIC;     -- AS input: DATAOUT, PS input: nSTATUS
		B_TCK  : BUFFER STD_LOGIC; -- JTAG output: TCK to chain, AS/PS DCLK
		B_TMS  : BUFFER STD_LOGIC; -- JTAG output: TMS to chain, AS/PS nCONFIG
		B_NCE  : BUFFER STD_LOGIC; -- AS output: nCE
		B_NCS  : BUFFER STD_LOGIC; -- AS output: nCS
		B_TDI  : BUFFER STD_LOGIC; -- JTAG output: TDI to chain, AS: ASDI, PS: DATA0
		B_OE   : BUFFER STD_LOGIC; -- LED output/output driver enable
		nRD : OUT STD_LOGIC;       -- FT245BM nRD
		WR : OUT STD_LOGIC;        -- FT245BM WR
		D : INOUT STD_LOGIC_VECTOR(7 downto 0) -- FT245BM D[7..0]
	);
END jtag_logic;

ARCHITECTURE spec OF jtag_logic IS

	-- There are exactly 16 states. If this is encoded using 4 bits, there will
	-- be no unknown/undefined state. The host will send us 64 times "0" to move
	-- the state machine to a known state. We don't need a power-on reset.

	TYPE states IS
	(
		wait_for_nRXF_low,
		set_nRD_low,
		keep_nRD_low,
		latch_data_from_host,
		set_nRD_high,
		bits_set_pins_from_data,
		bytes_set_bitcount,
		bytes_get_tdo_set_tdi,
		bytes_clock_high_and_shift,
		bytes_keep_clock_high,
		bytes_clock_finish,
		wait_for_nTXE_low,
		set_WR_high,
		output_enable,
		set_WR_low,
		output_disable
	);

	ATTRIBUTE ENUM_ENCODING: STRING;
	ATTRIBUTE ENUM_ENCODING OF states: TYPE IS
	  "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111";

	SIGNAL carry: STD_LOGIC;
	SIGNAL do_output: STD_LOGIC;
	SIGNAL ioshifter: STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL bitcount: STD_LOGIC_VECTOR(8 DOWNTO 0);
	SIGNAL state, next_state: states;

BEGIN
	sm: PROCESS(nRXF, nTXE, state, bitcount, ioshifter, do_output)

	BEGIN
		CASE state IS

			-- ============================ INPUT

			WHEN wait_for_nRXF_low =>
				IF nRXF='0' THEN
					next_state <= set_nRD_low;
				ELSE
					next_state <= wait_for_nRXF_low;
				END IF;

			WHEN set_nRD_low =>
				next_state <= keep_nRD_low;

			WHEN keep_nRD_low =>
				next_state <= latch_data_from_host;

			WHEN latch_data_from_host =>
				next_state <= set_nRD_high;

			WHEN set_nRD_high =>
				IF NOT (bitcount(8 DOWNTO 3) = "000000") THEN
					next_state <= bytes_get_tdo_set_tdi;
				ELSIF ioshifter(7) = '1' THEN
					next_state <= bytes_set_bitcount;
				ELSE
					next_state <= bits_set_pins_from_data;
				END IF;

			WHEN bytes_set_bitcount =>
				next_state <= wait_for_nRXF_low;

			-- ============================ BIT BANGING

			WHEN bits_set_pins_from_data =>
				IF ioshifter(6) = '0' THEN
					next_state <= wait_for_nRXF_low; -- read next byte from host
				ELSE
					next_state <= wait_for_nTXE_low; -- output byte to host
				END IF;

			-- ============================ BYTE OUTPUT (SHIFT OUT 8 BITS)

			WHEN bytes_get_tdo_set_tdi =>
				next_state <= bytes_clock_high_and_shift;

			WHEN bytes_clock_high_and_shift =>
				next_state <= bytes_keep_clock_high;

			WHEN bytes_keep_clock_high =>
				next_state <= bytes_clock_finish;

			WHEN bytes_clock_finish =>
				IF NOT (bitcount(2 DOWNTO 0) = "111") THEN
					next_state <= bytes_get_tdo_set_tdi; -- clock next bit
				ELSIF do_output = '1' THEN
					next_state <= wait_for_nTXE_low; -- output byte to host
				ELSE
					next_state <= wait_for_nRXF_low; -- read next byte from host
				END IF;

			-- ============================ OUTPUT BYTE TO HOST

			WHEN wait_for_nTXE_low =>
				IF nTXE = '0' THEN
					next_state <= set_WR_high;
				ELSE
					next_state <= wait_for_nTXE_low;
				END IF;

			WHEN set_WR_high =>
				next_state <= output_enable;

			WHEN output_enable =>
				next_state <= set_WR_low;

			WHEN set_WR_low =>
				next_state <= output_disable;

			WHEN output_disable =>
				next_state <= wait_for_nRXF_low; -- read next byte from host

			WHEN OTHERS =>
				next_state <= wait_for_nRXF_low;

		END CASE;
	END PROCESS sm;

	out_sm: PROCESS(CLK)

	BEGIN
		IF CLK = '1' AND CLK'event THEN

			IF state = set_nRD_low OR state = keep_nRD_low OR state = latch_data_from_host THEN
				nRD <= '0';
			ELSE
				nRD <= '1';
			END IF;

			IF state = latch_data_from_host THEN
				ioshifter(7 DOWNTO 0) <= D;
			END IF;

			IF state = set_WR_high OR state = output_enable THEN
				WR <= '1';
			ELSE
				WR <= '0';
			END IF;

			IF state = output_enable OR state = set_WR_low THEN
				D <= ioshifter(7 DOWNTO 0);
			ELSE
				D <= "ZZZZZZZZ";
			END IF;

			IF state = bits_set_pins_from_data THEN
				B_TCK <= ioshifter(0);
				B_TMS <= ioshifter(1);
				B_NCE <= ioshifter(2);
				B_NCS <= ioshifter(3);
				B_TDI <= ioshifter(4);
				B_OE  <= ioshifter(5);
				ioshifter <= "000000" & B_ASDO & B_TDO;
			END IF;

			IF state = bytes_set_bitcount THEN
				bitcount <= ioshifter(5 DOWNTO 0) & "111";
				do_output <= ioshifter(6);
			END IF;

			IF state = bytes_get_tdo_set_tdi THEN
				IF B_NCS = '1' THEN
					carry <= B_TDO; -- JTAG mode (nCS=1)
				ELSE
					carry <= B_ASDO; -- Active Serial mode (nCS=0)
				END IF;
				B_TDI <= ioshifter(0);
				bitcount <= bitcount - 1;
			END IF;

			IF state = bytes_clock_high_and_shift OR state = bytes_keep_clock_high THEN
				B_TCK <= '1';
			END IF;

			IF state = bytes_clock_high_and_shift THEN
				ioshifter <= carry & ioshifter(7 DOWNTO 1);
			END IF;

			IF state = bytes_clock_finish THEN
				B_TCK <= '0';
			END IF;

			state <= next_state;

		END IF;
	END PROCESS out_sm;

END spec;

TEXT 【X10】IntRangeとRegionの違い

public class RegionTest {
    public static def main(Array[String]) {
        val range  = 0..2;
        val region = (0..2) as Region(1);
        for(x in range) {
            Console.OUT.println("x = " + x); // x is Int
        }
        for(x in region) {
            Console.OUT.println("x = " + x); // x is Point
        }
    }
}

TEXT X10でハローワールド

public class Hello {
    public static def main(Array[String]) {
        finish for(pl in Place.places()) {
            async at(pl) Console.OUT.println(
                    "Hello world from place " + here.id);
        }
    }
}
Total Pages: 4 / 512345

よく投稿されているコード

タグ

最近投稿されたコード