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C Mapper080.sflp

/*
	Mapper 080
	Tatio X1-005
		PRG-ROM 16KB banks 8 16 max 256KB
		CHR-ROM 8KB banks 16 max 128KB
*/

circuit Mapper080
{
	// PRG-ROM
	input ROM_SELn;
	instrin prg_read, prg_write;
	input prg_A<15>, prg_Din<8>;
	output prg_Dout<8>;
	output IRQn;

	// CHR-ROM
	instrin chr_read, chr_write; // RDn, WEn
	input chr_A<14>;//, chr_Din<8>; // chr_A13n
	output chr_Dout<8>;
	output VRAM_CSn, VRAM_A10;

//	instrin Phi; // 1.789MHz
//	output usound<11>, ssound<14>;

	instrout exram_read(exram_adrs);
	output exram_adrs<13>; // EX_RAM  8KB
	output exram_wdata<8>;
	instrout exram_write(exram_adrs, exram_wdata);
	input exram_rdata<8>;

	// 外部RAMへのアクセス
	instrout prg_ram_read(prg_ram_adrs);
	output prg_ram_adrs<18>; // PRG_ROM max 256KB
//	output prg_ram_wdata<8>;
//	instrout prg_ram_write(prg_ram_adrs, prg_ram_wdata);
	input prg_ram_rdata<8>;

	instrout chr_ram_read(chr_ram_adrs);
	output chr_ram_adrs<17>; // CHR_ROM max 128KB
//	output chr_ram_wdata<8>;
//	instrout chr_ram_write(chr_ram_adrs, chr_ram_wdata);
	input chr_ram_rdata<8>;

	instrin init;

	input n16kRomBanks<6>, fMirroringType;
	reg_wr fMirroringType_reg;

	reg_wr prg_bank0<5>, prg_bank1<5>, prg_bank2<5>, prg_last_bank<5>;
	reg_wr chr_bank01<6>, chr_bank23<6>; // 偶数のみ
	reg_wr chr_bank4<7>, chr_bank5<7>, chr_bank6<7>, chr_bank7<7>;

	instrself map_rom, map_exram;

	sel prg_adrs<16>, prg_read_bank<5>;
	sel chr_read_bank<7>;

	par{

		if(ROM_SELn==0b0){
			map_rom();
		}
		else any{
		//	prg_A<14:13>==0b10 : map_exrom();
			prg_A<14:13>==0b11 : map_exram();
		}

		any{
			map_rom : prg_Dout = prg_ram_rdata;
			map_exram : prg_Dout = exram_rdata;
		}

		prg_adrs = 0b0 || prg_A;

		VRAM_CSn = ^chr_A<13>;

		if(fMirroringType_reg){
			// 垂直ミラー, 水平スクロールタイプ
			VRAM_A10 = chr_A<10>;
		}
		else{
			// 水平ミラー, 垂直スクロールタイプ
			VRAM_A10 = chr_A<11>;
		}

		chr_Dout = chr_ram_rdata;

		IRQn = 0b1;
/*
		usound = // <11>
		   0b00000000000;

		ssound = // <14s>
		   0b00000000000000;
*/
	}

	instruct init par{
		prg_bank0 := 0b00000;
		prg_bank1 := 0b00001;
		prg_bank2 :=     n16kRomBanks<4> || 0b1110;
		prg_last_bank := n16kRomBanks<4> || 0b1111;

		chr_bank01 := 0b000000; // 0x00
		chr_bank23 := 0b000001; // 0x02
		chr_bank4 := 0b000||0x4;
		chr_bank5 := 0b000||0x5;
		chr_bank6 := 0b000||0x6;
		chr_bank7 := 0b000||0x7;

		fMirroringType_reg := fMirroringType;
	}

	instruct prg_read any{
		map_rom : par{
			// prg_bank<5> + prg_A<13> = <18>
		//	sel prg_read_bank<5>;
			switch(prg_A<14:13>){
				case 0b00: prg_read_bank = prg_bank0;
				case 0b01: prg_read_bank = prg_bank1;
				case 0b10: prg_read_bank = prg_bank2;
				case 0b11: prg_read_bank = prg_last_bank;
			}
			prg_ram_read(prg_read_bank || prg_A<12:0>);
		}
		map_exram : exram_read(prg_A<12:0>);
	}

	instruct prg_write any{
		map_exram : switch(prg_adrs){
			case 0x7EF0: chr_bank01 := prg_Din<6:1>;
			case 0x7EF1: chr_bank23 := prg_Din<6:1>;
			case 0x7EF2: chr_bank4 := prg_Din<6:0>;
			case 0x7EF3: chr_bank5 := prg_Din<6:0>;
			case 0x7EF4: chr_bank6 := prg_Din<6:0>;
			case 0x7EF5: chr_bank7 := prg_Din<6:0>;
			case 0x7EF6: fMirroringType_reg := prg_Din<0>;
			(case 0x7EFA) | (case 0x7EFB): prg_bank0 := prg_Din<4:0>;
			(case 0x7EFC) | (case 0x7EFD): prg_bank1 := prg_Din<4:0>;
			(case 0x7EFE) | (case 0x7EFF): prg_bank2 := prg_Din<4:0>;
			default: exram_write(prg_A<12:0>, prg_Din);
		}
	}

	instruct chr_read par{
		if(chr_A<13>==0b0){
			// chr_bank<7> + chr_A<10> = <17>
			// sel chr_read_bank<7>;
			switch(chr_A<12:10>){
				case 0b000: chr_read_bank = chr_bank01 || 0b0;
				case 0b001: chr_read_bank = chr_bank01 || 0b1;
				case 0b010: chr_read_bank = chr_bank23 || 0b0;
				case 0b011: chr_read_bank = chr_bank23 || 0b1;
				case 0b100: chr_read_bank = chr_bank4;
				case 0b101: chr_read_bank = chr_bank5;
				case 0b110: chr_read_bank = chr_bank6;
				case 0b111: chr_read_bank = chr_bank7;
			}
			chr_ram_read(chr_read_bank || chr_A<9:0>);
		}
	}

}

C Mapper023.sflp

/*
	Mapper 023
	Konami VRC2 type B
		PRG-ROM 16KB banks 8 max 128KB
		CHR-ROM 8KB banks 16 32 max 256KB
*/

circuit Mapper023
{
	// PRG-ROM
	input ROM_SELn;
	instrin prg_read, prg_write;
	input prg_A<15>, prg_Din<8>;
	output prg_Dout<8>;
	output IRQn;

	// CHR-ROM
	instrin chr_read;//, chr_write; // RDn, WEn
	input chr_A<14>;//, chr_Din<8>; // chr_A13n
	output chr_Dout<8>;
	output VRAM_CSn, VRAM_A10;

//	instrin Phi; // 1.789MHz
//	output usound<11>, ssound<14>;

	instrout exram_read(exram_adrs);
	output exram_adrs<13>; // EX_RAM  8KB
	output exram_wdata<8>;
	instrout exram_write(exram_adrs, exram_wdata);
	input exram_rdata<8>;

	instrout prg_ram_read(prg_ram_adrs);
	output prg_ram_adrs<17>; // PRG_ROM max 128KB
//	output prg_ram_wdata<8>;
//	instrout prg_ram_write(prg_ram_adrs, prg_ram_wdata);
	input prg_ram_rdata<8>;

	instrout chr_ram_read(chr_ram_adrs);
	output chr_ram_adrs<18>; // CHR_ROM max 256KB
//	output chr_ram_wdata<8>;
//	instrout chr_ram_write(chr_ram_adrs, chr_ram_wdata);
	input chr_ram_rdata<8>;

	instrin init;
	instrin hblank;

	input fMirroringType;
	reg_wr fMirroringType_reg<2>;

	sel prg_adrs<8>;
	reg_wr prg_bank4<4>, prg_bank5<4>, prg_bank6<4>, prg_last_bank<4>;
	reg_wr chr_bank0_L<4>, chr_bank1_L<4>, chr_bank2_L<4>, chr_bank3_L<4>;
	reg_wr chr_bank4_L<4>, chr_bank5_L<4>, chr_bank6_L<4>, chr_bank7_L<4>;
	reg_wr chr_bank0_H<4>, chr_bank1_H<4>, chr_bank2_H<4>, chr_bank3_H<4>;
	reg_wr chr_bank4_H<4>, chr_bank5_H<4>, chr_bank6_H<4>, chr_bank7_H<4>;

	instrself map_rom, map_exram;

	reg_ws IRQn_reg;
	reg_wr regs_8<2>;

	reg_wr irq_counter<8>, irq_enabled<2>; //irq_clock<8>;
	reg_wr irq_latch_H<4>, irq_latch_L<4>;

	sel prg_read_bank<4>;
	sel chr_read_bank<8>;

	par{
		if(ROM_SELn==0b0){
			map_rom();
		}
		else any{
		//	prg_A<14:13>==0b10 : map_exrom();
			prg_A<14:13>==0b11 : map_exram();
		}

		any{
			map_rom : prg_Dout = prg_ram_rdata;
			map_exram : prg_Dout = exram_rdata;
		}

		prg_adrs = 0b1 || prg_A<14:12> || prg_A<3:0>; // 1111_----_----_1111

		VRAM_CSn = ^chr_A<13>;

		switch(fMirroringType_reg){
			case 0b00: VRAM_A10 = chr_A<10>;
			case 0b01: VRAM_A10 = chr_A<11>;
			case 0b10: VRAM_A10 = 0b0; // mirror $2000
			case 0b11: VRAM_A10 = 0b1; // mirror $2400
		}

		chr_Dout = chr_ram_rdata;

		IRQn = IRQn_reg;
	}

	instruct init par{
		regs_8 := 0b00;
		prg_bank4 := 0b0000;
		prg_bank5 := 0b0001;
		prg_bank6     := 0b1110;
		prg_last_bank := 0b1111;
		irq_latch_L := 0;
		irq_latch_H := 0;
		irq_counter := 0;
		irq_enabled := 0;
		chr_bank0_L := 0x0; chr_bank0_H := 0x0;
		chr_bank1_L := 0x1; chr_bank1_H := 0x0;
		chr_bank2_L := 0x2; chr_bank2_H := 0x0;
		chr_bank3_L := 0x3; chr_bank3_H := 0x0;
		chr_bank4_L := 0x4; chr_bank4_H := 0x0;
		chr_bank5_L := 0x5; chr_bank5_H := 0x0;
		chr_bank6_L := 0x6; chr_bank6_H := 0x0;
		chr_bank7_L := 0x7; chr_bank7_H := 0x0;
		fMirroringType_reg := 0b0 || ^fMirroringType;
	}

	instruct prg_read any{
		map_rom : par{
			// prg_bank<4> + prg_A<13> = <17>
//			sel prg_read_bank<4>;
			switch(prg_A<14:13>){
				case 0b00: prg_read_bank = prg_bank4;
				case 0b01: prg_read_bank = prg_bank5;
				case 0b10: prg_read_bank = prg_bank6;
				case 0b11: prg_read_bank = prg_last_bank;
			}
			prg_ram_read(prg_read_bank<3:0> || prg_A<12:0>);
		}
		map_exram : exram_read(prg_A<12:0>);
	}

	instruct prg_write any{
		map_rom : switch(prg_adrs){
			(case 0x80) | (case 0x84) |
			(case 0x88) | (case 0x8C) : par{
				if(/|regs_8) prg_bank6 := prg_Din<3:0>;
				else         prg_bank4 := prg_Din<3:0>;
			}
			case 0x90 : fMirroringType_reg := prg_Din<1:0>;
			case 0x98 : regs_8 := prg_Din<1:0>;
			(case 0xA0) | (case 0xA4) |
			(case 0xA8) | (case 0xAC) : prg_bank5 := prg_Din<3:0>;
			case 0xB0 :                 chr_bank0_L := prg_Din<3:0>;
			(case 0xB1) | (case 0xB4) : chr_bank0_H := prg_Din<3:0>;
			(case 0xB2) | (case 0xB8) : chr_bank1_L := prg_Din<3:0>;
			(case 0xB3) | (case 0xBC) : chr_bank1_H := prg_Din<3:0>;
			case 0xC0 :                 chr_bank2_L := prg_Din<3:0>;
			(case 0xC1) | (case 0xC4) : chr_bank2_H := prg_Din<3:0>;
			(case 0xC2) | (case 0xC8) : chr_bank3_L := prg_Din<3:0>;
			(case 0xC3) | (case 0xCC) : chr_bank3_H := prg_Din<3:0>;
			case 0xD0 :                 chr_bank4_L := prg_Din<3:0>;
			(case 0xD1) | (case 0xD4) : chr_bank4_H := prg_Din<3:0>;
			(case 0xD2) | (case 0xD8) : chr_bank5_L := prg_Din<3:0>;
			(case 0xD3) | (case 0xDC) : chr_bank5_H := prg_Din<3:0>;
			case 0xE0 :                 chr_bank6_L := prg_Din<3:0>;
			(case 0xE1) | (case 0xE4) : chr_bank6_H := prg_Din<3:0>;
			(case 0xE2) | (case 0xE8) : chr_bank7_L := prg_Din<3:0>;
			(case 0xE3) | (case 0xEC) : chr_bank7_H := prg_Din<3:0>;
			case 0xF0 : irq_latch_L := prg_Din<3:0>;
			case 0xF4 : irq_latch_H := prg_Din<3:0>;
			case 0xF8 : par{
				irq_enabled := prg_Din<1:0>;
				if(prg_Din<1>) irq_counter := irq_latch_H || irq_latch_L;
			}
			case 0xFC : irq_enabled := 2#irq_enabled<0>;
			(prg_adrs<7:4>==0xF) : IRQn_reg := 0b1;
		}
		map_exram : exram_write(prg_A<12:0>, prg_Din);
	}

	instruct chr_read par{
		if(chr_A<13>==0b0){
			// chr_bank<8> + chr_A<10> = <18>
//			sel chr_read_bank<8>;
			switch(chr_A<12:10>){
				case 0b000: chr_read_bank = chr_bank0_H || chr_bank0_L;
				case 0b001: chr_read_bank = chr_bank1_H || chr_bank1_L;
				case 0b010: chr_read_bank = chr_bank2_H || chr_bank2_L;
				case 0b011: chr_read_bank = chr_bank3_H || chr_bank3_L;
				case 0b100: chr_read_bank = chr_bank4_H || chr_bank4_L;
				case 0b101: chr_read_bank = chr_bank5_H || chr_bank5_L;
				case 0b110: chr_read_bank = chr_bank6_H || chr_bank6_L;
				case 0b111: chr_read_bank = chr_bank7_H || chr_bank7_L;
			}
			chr_ram_read(chr_read_bank || chr_A<9:0>);
		}
	}

	instruct hblank par{
		if(irq_enabled<1>){
			if(/&irq_counter){
				IRQn_reg := 0b0;
				irq_counter := irq_latch_H || irq_latch_L;
				irq_enabled := 2#irq_enabled<0>;
			}
			else irq_counter++;
		}
	}

}

C Mapper016.sflp

/*
	Mapper 016
	Bandai chip
		PRG-ROM 16KB banks 8 16 32 max 512KB
		CHR-ROM 8KB banks 4 (8) 16 32 max 256KB
*/

circuit Mapper016
{
	// PRG-ROM
	input ROM_SELn;
	instrin prg_read, prg_write;
	input prg_A<15>, prg_Din<8>;
	output prg_Dout<8>;
	output IRQn;

	// CHR-ROM
	instrin chr_read, chr_write; // RDn, WEn
	input chr_A<14>, chr_Din<8>; // chr_A13n
	output chr_Dout<8>;
	output VRAM_CSn, VRAM_A10;

	instrout exram_read(exram_adrs);
	output exram_adrs<13>; // EX_RAM  8KB
	output exram_wdata<8>;
	instrout exram_write(exram_adrs, exram_wdata);
	input exram_rdata<8>;

	// 外部RAMへのアクセス
	instrout prg_ram_read(prg_ram_adrs);
	output prg_ram_adrs<19>; // PRG_ROM max 512KB
//	output prg_ram_wdata<8>;
//	instrout prg_ram_write(prg_ram_adrs, prg_ram_wdata);
	input prg_ram_rdata<8>;

	instrout chr_ram_read(chr_ram_adrs);
	output chr_ram_adrs<18>; // CHR_ROM max 256KB
//	output chr_ram_wdata<8>;
//	instrout chr_ram_write(chr_ram_adrs, chr_ram_wdata);
	input chr_ram_rdata<8>;

	instrin init;
	instrin hblank;

	input n16kRomBanks<6>, n8kVRomBanks<6>, fMirroringType;
	reg_wr fMirroringType_reg<2>;

	reg_wr prg_bank0<6>, prg_bank1<6>, prg_last_bank<5>;
	reg_wr chr_bank0<8>, chr_bank1<8>, chr_bank2<8> ,chr_bank3<8>;
	reg_wr chr_bank4<8>, chr_bank5<8>, chr_bank6<8>, chr_bank7<8>;

	instrself map_rom, map_exrom, map_exram;

	reg_ws IRQn_reg;
	reg_wr irq_counter<16>, irq_latch_L<8>, irq_latch_H<8>, irq_enabled;

	sel prg_read_bank<6>;
	sel chr_read_bank<8>;

	par{

		if(ROM_SELn==0b0){
			map_rom();
		}
		else any{
			prg_A<14:13>==0b10 : map_exrom();
			prg_A<14:13>==0b11 : map_exram();
		}

		any{
			map_rom : prg_Dout = prg_ram_rdata;
			map_exram : prg_Dout = exram_rdata;
		}

		VRAM_CSn = ^chr_A<13>;

		switch(fMirroringType_reg){
			case 0b00: VRAM_A10 = chr_A<11>; // 水平ミラー, 垂直スクロールタイプ
			case 0b01: VRAM_A10 = chr_A<10>; // 垂直ミラー, 水平スクロールタイプ
			case 0b10: VRAM_A10 = 0b0; // mirror $2000
			case 0b11: VRAM_A10 = 0b1; // mirror $2400
		}

		// chr_bank<8> + chr_A<10> = <18>
	//	sel chr_read_bank<8>;
		switch(chr_A<12:10>){
			case 0b000: chr_read_bank = chr_bank0;
			case 0b001: chr_read_bank = chr_bank1;
			case 0b010: chr_read_bank = chr_bank2;
			case 0b011: chr_read_bank = chr_bank3;
			case 0b100: chr_read_bank = chr_bank4;
			case 0b101: chr_read_bank = chr_bank5;
			case 0b110: chr_read_bank = chr_bank6;
			case 0b111: chr_read_bank = chr_bank7;
		}

		chr_Dout = chr_ram_rdata;

		IRQn = IRQn_reg;
	}

	instruct init par{
		prg_bank0 := 0b000000;
		prg_bank1 := 0b000001;
		prg_last_bank := (n16kRomBanks - 0b000001)<4:0>;
		irq_counter := 0;
		irq_latch_L := 0;
		irq_latch_H := 0;
		irq_enabled := 0;

		chr_bank0 := 0x00;
		chr_bank1 := 0x01;
		chr_bank2 := 0x02;
		chr_bank3 := 0x03;
		chr_bank4 := 0x04;
		chr_bank5 := 0x05;
		chr_bank6 := 0x06;
		chr_bank7 := 0x07;

		fMirroringType_reg := 0b0 || ^fMirroringType;

		IRQn_reg := 0b1;
	}

	instruct prg_read any{
		map_rom : par{
			// prg_bank<6> + prg_A<13> = <19>
		//	sel prg_read_bank<6>;
			switch(prg_A<14:13>){
				case 0b00: prg_read_bank = prg_bank0;
				case 0b01: prg_read_bank = prg_bank1;
				case 0b10: prg_read_bank = prg_last_bank || 0b0;
				case 0b11: prg_read_bank = prg_last_bank || 0b1;
			}
			prg_ram_read(prg_read_bank || prg_A<12:0>);
		}
		map_exram : exram_read(prg_A<12:0>);
	}

	instruct prg_write any{
		map_rom : par{
			switch(prg_A<3:0>){
				case 0x0: chr_bank0 := prg_Din;
				case 0x1: chr_bank1 := prg_Din;
				case 0x2: chr_bank2 := prg_Din;
				case 0x3: chr_bank3 := prg_Din;
				case 0x4: chr_bank4 := prg_Din;
				case 0x5: chr_bank5 := prg_Din;
				case 0x6: chr_bank6 := prg_Din;
				case 0x7: chr_bank7 := prg_Din;
				case 0x8: par{
					prg_bank0 := prg_Din<4:0> || 0b0;
					prg_bank1 := prg_Din<4:0> || 0b1;
				}
				case 0x9: fMirroringType_reg := prg_Din<1:0>;
				case 0xA: par{
					irq_enabled := prg_Din<0>;
					irq_counter := irq_latch_H || irq_latch_L;
					IRQn_reg := 0b1;
				}
				case 0xB: irq_latch_L := prg_Din;
				case 0xC: irq_latch_H := prg_Din;
			}
		}
		map_exram : exram_write(prg_A<12:0>, prg_Din);
	}

	instruct chr_read par{
		if(chr_A<13>==0b0){
			chr_ram_read(chr_read_bank || chr_A<9:0>);
		}
	}

	instruct hblank par{
		if(irq_enabled){
			if(irq_counter<15>){
				IRQn_reg := 0b0;
				irq_enabled := 0b0;
			}
			else irq_counter -= 113;
		}
	}
}

C mem_8x2k.sflp

%i "ram_8x2k.h"

circuit mem_8x2k
{
	input adrs<11>, din<8>;
	output dout<8>;
	instrin read(adrs);
	instrin write(adrs, din);

	ram_8x2k ram;

	instrin init;

	stage_name init_stg { task do(); }

	par{
		dout = ram.dout;
	}

	instruct read ram.read(adrs);
	instruct write ram.write(adrs, din);
	instruct init init_stg.do();

	stage init_stg {
		reg_wr mem_adrs<11>;
		par{
			ram.write(mem_adrs, 0x00);
			mem_adrs++;
			if(/&mem_adrs) finish;
		}
	}
}

C nsl test

if(~spi_read & ~spi_write){
	if(select && rd == 1'b0){
		spi_read();
	}else if(select && wr == 1'b0){
		spi_write();
	}
}

C sdcard_spiport

declare sdcard_spiport{
	input select, rd, wr, bytemask[2];
	input d[16]; output q[16], cpu_wait;
	input spi_do; output spi_clk, spi_di;
}

//spi clock frequency is 64MHz / 4 って書いてたけど 64MHz / 8 になってる
module sdcard_spiport
{
	proc_name spi_read, spi_write;
	reg spi_clock = 0, r_wait = 0;
	reg serial_count[4], divide_count[2];
	reg writedata[16], readdata[16];

	if(select && rd == 1'b0){
		spi_read();
	}else if(select && wr == 1'b0){
		spi_write();
	}

	spi_clk = spi_clock;
	spi_di = writedata[15];
	q = readdata;
	cpu_wait = r_wait;

	proc spi_read{
		state_name read_init, read_l, read_h, read_end;
		state read_init{
			writedata := 16'hffff;
			divide_count := 0;
			spi_clock := 0;
			if(bytemask == 2'b00){
				serial_count := 15;
				goto read_l;
			}else if(bytemask == 2'b11){
				r_wait := 1;
				goto read_end;
			}else{
				serial_count := 7;
				goto read_l;
			}
		}
		state read_l{
			divide_count := divide_count + 1;
			if(divide_count == 2'b11){
				readdata := {readdata[14:0], spi_do};
				spi_clock := 1;
				goto read_h;
			}
		}
		state read_h{
			divide_count := divide_count + 1;
			if(divide_count == 2'b11){
				spi_clock := 0;
				if(serial_count == 0){
					r_wait := 1;
					goto read_end;
				}else{
					serial_count := serial_count - 1;
					goto read_l;
				}
			}
		}
		state read_end{
			if(rd == 1'b1){
				r_wait := 0;
				finish();
				goto read_init;
			}
		}
	}

	proc spi_write{
		state_name write_init, write_wait_0, write_wait_1, write_l, write_h, write_end;
		state write_init{
			divide_count := 0;
			spi_clock := 0;
			if(bytemask == 2'b00){
				serial_count := 15;
				goto write_wait_0;
			}else if(bytemask == 2'b11){
				r_wait := 1;
				goto write_end;
			}else{
				serial_count := 7;
				goto write_wait_0;
			}
		}
		//databus 確定のため2clock待つ
		state write_wait_0{
			goto write_wait_1;
		}
		state write_wait_1{
			if(bytemask == 2'b00){
				writedata := d;
			}else{
				writedata := {d[7:0], 8'h00};
			}
			goto write_l;
		}
		state write_l{
			divide_count := divide_count + 1;
			if(divide_count == 2'b11){
				spi_clock := 1;
				goto write_h;
			}
		}
		state write_h{
			divide_count := divide_count + 1;
			if(divide_count == 2'b11){
				writedata := {writedata[14:0], 1'b1};
				spi_clock := 0;
				if(serial_count == 0){
					r_wait := 1;
					goto write_end;
				}else{
					serial_count := serial_count - 1;
					goto write_l;
				}
			}
		}
		state write_end{
			if(wr == 1){
				r_wait := 0;
				finish();
				goto write_init;
			}
		}
	}
}

C シフト演算すると0が入るんですよ

void segcopy(int index, const void *src, uint16_t length);

static void font_trans(uint16_t destseg)
{
#define FONT1BPPSIZE (4 * 0x40)
	static const uint16_t font1bpp [] = {
		#include "font1bpp.inc"
	};
	const uint16_t *f1 = font1bpp;
	uint16_t font4bpp[FONT1BPPSIZE * 4];
	uint16_t *f4 = font4bpp;
	int length = FONT1BPPSIZE;

	while(length != 0){
		uint16_t pt1 = *f1++;
		uint16_t pt4 = 0; //初期化しなくていいけど warning がでる
		int i;
		for(i = 0; i < 16; i++){
			pt4 <<= 4;
			if(pt1 & 0x8000){
				pt4 |= 2;
			}
			pt1 <<= 1;

			if((i & 3) == 3){
				*f4++ = pt4;
			}
		}
		length--;
	}
	segcopy(destseg/*ax*/, font4bpp/*bx*/, FONT1BPPSIZE * 4 /*cx*/);
#undef FONT1BPPSIZE
}

C Mapper019.sflp

/*
	Mapper 019
	Namcot 106/163
		PRG-ROM 16KB banks 2 (4) 8 16 32 max 512KB
		CHR-ROM 8KB banks 16 32 max 256KB
		CHR-RAM (nes.nsf)
*/

%i "n106/n106_core.h"

circuit Mapper019
{
	// PRG-ROM
	input ROM_SELn;
	instrin prg_read, prg_write;
	input prg_A<15>, prg_Din<8>;
	output prg_Dout<8>;
	output IRQn;

	// CHR-ROM
	instrin chr_read, chr_write; // RDn, WEn
	input chr_A<14>, chr_Din<8>; // chr_A13n
	output chr_Dout<8>;
	output VRAM_CSn, VRAM_A10;

	instrin Phi; // 1.789MHz
	output usound<11>, ssound<14>;

	instrout exram_read(exram_adrs);
	output exram_adrs<13>; // EX_RAM 8KB
	output exram_wdata<8>;
	instrout exram_write(exram_adrs, exram_wdata);
	input exram_rdata<8>;

	// 外部RAMへのアクセス
	instrout prg_ram_read(prg_ram_adrs);
	output prg_ram_adrs<19>; // PRG_ROM max 512KB
//	output prg_ram_wdata<8>;
//	instrout prg_ram_write(prg_ram_adrs, prg_ram_wdata);
	input prg_ram_rdata<8>;

	instrout chr_ram_read(chr_ram_adrs);
	output chr_ram_adrs<18>; // CHR_ROM max 256KB
	output chr_ram_wdata<8>;
	instrout chr_ram_write(chr_ram_adrs, chr_ram_wdata);
	input chr_ram_rdata<8>;

	instrin ready, init;
	instrin hblank;

	input n16kRomBanks<6>, n8kVRomBanks<6>, fMirroringType;

	reg_wr prg_bank4<6>, prg_bank5<6>, prg_bank6<6>, prg_bank7<6>;
	reg_wr chr_bank0<8>, chr_bank1<8>, chr_bank2<8>, chr_bank3<8>;
	reg_wr chr_bank4<8>, chr_bank5<8>, chr_bank6<8>, chr_bank7<8>;
	reg_wr chr_bank8<8>, chr_bank9<8>, chr_bank10<8>, chr_bank11<8>;

	instrself map_rom, map_exrom, map_exram;

	reg_ws IRQn_reg;

	n106_core n106;

	reg_wr regs0, regs1;
	reg_wr irq_counter_L<8>, irq_counter_H<8>, irq_enabled;

	reg_wr prg_mask<6>, chr_mask<8>;
	sel prg_read_bank<6>, chr_bank<8>;
	sel irq_counter_s<16>;

	par{
		if(ROM_SELn==0b0){
			map_rom();
		}
		else any{
			prg_A<14:13>==0b10 : map_exrom();
			prg_A<14:13>==0b11 : map_exram();
		}

		any{
			map_exrom : any{
				prg_A<12:10>==0b010 : par{ // $4800
					prg_Dout = n106.io_Dout;
				}
			}
			map_exram : prg_Dout = exram_rdata;
			map_rom : prg_Dout = prg_ram_rdata;
		}

		if(chr_A<13>==0b0){
			// chr_bank<8> + chr_A<10> = <18>
		//	sel chr_read_bank<8>;
			switch(chr_A<12:10>){
				case 0b000: chr_bank = chr_bank0;
				case 0b001: chr_bank = chr_bank1;
				case 0b010: chr_bank = chr_bank2;
				case 0b011: chr_bank = chr_bank3;
				case 0b100: chr_bank = chr_bank4;
				case 0b101: chr_bank = chr_bank5;
				case 0b110: chr_bank = chr_bank6;
				case 0b111: chr_bank = chr_bank7;
			}
			VRAM_CSn = 0b1;
		}
		else{ // NameTable or CHR-ROM
			switch(chr_A<11:10>){
				case 0b00: par{
					if(/&chr_bank8<7:5>){
						VRAM_CSn = 0b0;
						VRAM_A10 = chr_bank8<0>;
					}
					else{
						VRAM_CSn = 0b1;
						chr_bank = chr_bank8;
					}
				}
				case 0b01: par{
					if(/&chr_bank9<7:5>){
						VRAM_CSn = 0b0;
						VRAM_A10 = chr_bank9<0>;
					}
					else{
						VRAM_CSn = 0b1;
						chr_bank = chr_bank9;
					}
				}
				case 0b10: par{
					if(/&chr_bank10<7:5>){
						VRAM_CSn = 0b0;
						VRAM_A10 = chr_bank10<0>;
					}
					else{
						VRAM_CSn = 0b1;
						chr_bank = chr_bank10;
					}
				}
				case 0b11: par{
					if(/&chr_bank11<7:5>){
						VRAM_CSn = 0b0;
						VRAM_A10 = chr_bank11<0>;
					}
					else{
						VRAM_CSn = 0b1;
						chr_bank = chr_bank11;
					}
				}
			}
		}

		chr_Dout = chr_ram_rdata;

		IRQn = IRQn_reg;

		usound = // <11>
			0b00 || n106.sound || 0b00;

		ssound = // <14s>
		   0b00000000000000;
	}

	instruct ready n106.ready();

	instruct init par{
		prg_bank4 := 0b000000;
		prg_bank5 := 0b000001;
		prg_bank6 := 0b111110; //(n16kRomBanks - 0b000001)<4:0> || 0b0;
		prg_bank7 := 0b111111; //(n16kRomBanks - 0b000001)<4:0> || 0b1;
		prg_mask  := (n16kRomBanks - 0b000001)<4:0> || 0b1;
		irq_counter_L := 0;
		irq_counter_H := 0;
		irq_enabled := 0;
		chr_bank0 := 0x00;
		chr_bank1 := 0x01;
		chr_bank2 := 0x02;
		chr_bank3 := 0x03;
		chr_bank4 := 0x04;
		chr_bank5 := 0x05;
		chr_bank6 := 0x06;
		chr_bank7 := 0x07;
		chr_mask := (n8kVRomBanks - 0b000001)<4:0> || 0b111;
		if(fMirroringType){
			chr_bank8 := 0x00;
			chr_bank9 := 0x01;
			chr_bank10 := 0x00;
			chr_bank11 := 0x01;
		}
		else{
			chr_bank8 := 0x00;
			chr_bank9 := 0x00;
			chr_bank10 := 0x01;
			chr_bank11 := 0x01;
		}
		regs0 := 0b0;
		regs1 := 0b0;
	}

	instruct prg_read any{
		map_exrom : par{
			switch(prg_A<12:11>){
				case 0b01: par{ // $4800
					n106.io_read(0b0);
				}
				case 0b10: par{ // $5000
					prg_Dout = irq_counter_L;
				}
				case 0b11: par{ // $5800
					prg_Dout = 0b0 || irq_counter_H<6:0>;
				}
				default: prg_Dout = 0b0 || prg_A<14:8>;
			}
		}
		map_rom : par{
			// prg_bank<6> + prg_A<13> = <19>
		//	sel prg_read_bank<6>;
			switch(prg_A<14:13>){
				case 0b00: prg_read_bank = prg_bank4;
				case 0b01: prg_read_bank = prg_bank5;
				case 0b10: prg_read_bank = prg_bank6;
				case 0b11: prg_read_bank = prg_bank7;
			}
			prg_ram_read((prg_read_bank & prg_mask) || prg_A<12:0>);
		}
		map_exram : exram_read(prg_A<12:0>);
	}

	instruct prg_write any{
		map_exrom : par{
			switch(prg_A<12:11>){
				case 0b01: par{ // $4800
					n106.io_write(0b0, prg_Din);
				}
				case 0b10: par{ // $5000
					irq_counter_L := prg_Din;
					IRQn_reg := 0b1;
				}
				case 0b11: par{ // $5800
					irq_counter_H := 0b0 || prg_Din<6:0>;
					irq_enabled := prg_Din<7>;
					IRQn_reg := 0b1;
				}
			}
		}
		map_rom : par{
			switch(prg_A<14:11>){
				case 0b0000: par{ // $8000
					if((prg_Din<7:5>!=0b111) | regs0) chr_bank0 := prg_Din;
					else chr_bank0 := 0x00;
				}
				case 0b0001: par{ // $8800
					if((prg_Din<7:5>!=0b111) | regs0) chr_bank1 := prg_Din;
					else chr_bank1 := 0x01;
				}
				case 0b0010: par{ // $9000
					if((prg_Din<7:5>!=0b111) | regs0) chr_bank2 := prg_Din;
					else chr_bank2 := 0x02;
				}
				case 0b0011: par{ // $9800
					if((prg_Din<7:5>!=0b111) | regs0) chr_bank3 := prg_Din;
					else chr_bank3 := 0x03;
				}
				case 0b0100: par{ // $A000
					if((prg_Din<7:5>!=0b111) | regs1) chr_bank4 := prg_Din;
					else chr_bank4 := 0x04;
				}
				case 0b0101: par{ // $A800
					if((prg_Din<7:5>!=0b111) | regs1) chr_bank5 := prg_Din;
					else chr_bank5 := 0x05;
				}
				case 0b0110: par{ // $B000
					if((prg_Din<7:5>!=0b111) | regs1) chr_bank6 := prg_Din;
					else chr_bank6 := 0x06;
				}
				case 0b0111: par{ // $B800
					if((prg_Din<7:5>!=0b111) | regs1) chr_bank7 := prg_Din;
					else chr_bank7 := 0x07;
				}
				case 0b1000: par{ // $C000
					chr_bank8 := prg_Din;
				}
				case 0b1001: par{ // $C800
					chr_bank9 := prg_Din;
				}
				case 0b1010: par{ // $D000
					chr_bank10 := prg_Din;
				}
				case 0b1011: par{ // $D800
					chr_bank11 := prg_Din;
				}
				case 0b1100: par{ // $E000
					prg_bank4 := prg_Din<5:0>;
				}
				case 0b1101: par{ // $E800
					prg_bank5 := prg_Din<5:0>;
					regs0 := prg_Din<6>;
					regs1 := prg_Din<7>;
				}
				case 0b1110: par{ // $F000
					prg_bank6 := prg_Din<5:0>;
				}
				case 0b1111: par{ // $F800
					n106.io_write(0b1, prg_Din);
				}
			}
		}
		map_exram : /*if(fSaveRAMenable)*/ exram_write(prg_A<12:0>, prg_Din);
	}

	instruct chr_read par{
		if(VRAM_CSn==0b1){
			chr_ram_read((chr_bank & chr_mask) || chr_A<9:0>);
		}
	}

	instruct chr_write par{
		if(VRAM_CSn==0b1){
			chr_ram_write((chr_bank & chr_mask) || chr_A<9:0>, chr_Din);
		}
	}

	instruct Phi n106.run();

	instruct hblank par{
		if(irq_enabled){
			if(irq_counter_H<7>){
				irq_counter_L := 0xFF;
				irq_counter_H := 0x7F;
				IRQn_reg := 0b0;
				irq_enabled := 0b0;
			}
			else{
				irq_counter_s = (irq_counter_H||irq_counter_L) + 0x0071;
				irq_counter_L := irq_counter_s<7:0>;
				irq_counter_H := irq_counter_s<15:8>;
			}
		}
	}

}

C C言語で作る、はじめてのDAWソフト制作

#include <stdio.h>
#include <math.h>

int main(void)
{
	int i, j;
	unsigned char header[44] = {0x52, 0x49, 0x46, 0x46, 0x34, 0xb1, 0x02, 0x00, 0x57, 0x41, 0x56, 0x45, 0x66, 0x6d, 0x74, 0x20, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x44, 0xac, 0x00, 0x00, 0x44, 0xac, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x64, 0x61, 0x74, 0x61, 0x10, 0xb1, 0x02, 0x00};
	FILE *fp = fopen("out.wav", "wb");
	double x = 0.0f;
	double y = 0.0f;
	double z = 0.0f;
	unsigned char buff[44100/4] = {0};
	int p = 0;

	fwrite(header, 1, 44, fp);

	for(i=0; i<16; i++)
	{
		int key;
		scanf("%d", &key);
		for(j=0; j<44100/4; j++)
		{
			unsigned char a = ((unsigned char)((sin(x) >= 0.0 ? 1.0 : -1.0) * 64.0 + sin(z) * 63.0 + 128.0) + buff[p] * 3) / 4;
			buff[p] = a;
			p = (p + 1) % (44100 / 4);
			fwrite(&a, 1, 1, fp);
			x += (441.0 + sin(y) * 10.0) * pow(2.0, (double)key / 12.0) * 2.0 * 3.14159265358979 / 44100.0;
			y += 5.0 * 2.0 * 3.14159265358979 / 44100.0;
			z += (441.0 + sin(y) * 10.0) * pow(2.0, (double)(key + 7) / 12.0) * 2.0 * 3.14159265358979 / 44100.0;
		}
	}
	fclose(fp);
	return 0;
}

C sprite renderer の一部

		state pattern_load{
			if(vram_ready == 1'b0){
				vram_read := 1;
				if(x_axis[0] == 1'b0 && x_flip == 1'b0){
					lb0_d := vram_d[31:28];
					lb1_d := vram_d[27:24];
					pattern := {vram_d[23:0], 4'h0};
				}else if(x_axis[0] == 1'b0 && x_flip == 1'b1){
					lb0_d := vram_d[3:0];
					lb1_d := vram_d[7:4];
					pattern := {vram_d[11:8], vram_d[15:12], vram_d[19:16], vram_d[23:20], vram_d[27:24], vram_d[31:28], 4'h0};
				}else if(x_axis[0] == 1'b1 && x_flip == 1'b0){
					lb0_d := pattern[27:24];
					lb1_d := vram_d[31:28];

					pattern := vram_d[27:0];
				}if(x_axis[0] == 1'b1 && x_flip == 1'b1){
					lb0_d := pattern[27:24];
					lb1_d := vram_d[3:0];

					pattern := {vram_d[7:4], vram_d[11:8], vram_d[15:12], vram_d[19:16], vram_d[23:20], vram_d[27:24], vram_d[31:28]};
				}
/* この不定値設定が悪かったみたい
				else{
					pattern := 28'hx;
				}*/
				goto render_next;
			}
		}
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