C++に投稿されたコード一覧

C++ make_png.cpp

#include<stdio.h>
#include<stdlib.h>

#include<fcntl.h>

#pragma comment(lib, "../pngmake/zlib.lib")
#pragma comment(lib, "../pngmake/libpng.lib")

//#ifdef _MSC_VER	//VC++でのコンパイル
#include<io.h>
#include "../pngmake/png.h"
//#else
//#include <png.h>
//#endif

#define WIDTH 256
#define HEIGHT 224

void write_png(const char *file_name, unsigned char **image, int iWidth, int iHeight)
{
	FILE            *fp;
	png_structp     png_ptr;
	png_infop       info_ptr;

	fp = fopen(file_name, "wb");                            // まずファイルを開きます
	png_ptr = png_create_write_struct(                      // png_ptr構造体を確保・初期化します
	                PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
	info_ptr = png_create_info_struct(png_ptr);             // info_ptr構造体を確保・初期化します
	png_init_io(png_ptr, fp);                               // libpngにfpを知らせます
	png_set_IHDR(png_ptr, info_ptr, iWidth, iHeight,          // IHDRチャンク情報を設定します
	                8, PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE,
	                PNG_COMPRESSION_TYPE_DEFAULT, PNG_FILTER_TYPE_DEFAULT);
	png_write_info(png_ptr, info_ptr);                      // PNGファイルのヘッダを書き込みます
	png_write_image(png_ptr, image);                        // 画像データを書き込みます
	png_write_end(png_ptr, info_ptr);                       // 残りの情報を書き込みます
	png_destroy_write_struct(&png_ptr, &info_ptr);          // 2つの構造体のメモリを解放します
	fclose(fp);                                             // ファイルを閉じます
	return;
}

int main()//char *argv[], int argc)
{
	char *argv[] = {"", "out.dat", "out.png"};
	int argc = 3;

	int i;
	unsigned char **image;      // image[HEIGHT][WIDTH]の形式です
	FILE *fp;

	int x,y;
	char buf[1024];

	if(argc!=3){
		printf("option err\n");
		return -1;
	}

	image = (unsigned char**)malloc(sizeof(png_bytep)*HEIGHT); // 以下3行は2次元配列を確保します
	for(i=0; i<HEIGHT; i++){
		image[i] = (unsigned char*)malloc(sizeof(png_byte)*WIDTH*3);
	}

	fp = fopen(argv[1], "r");
	if(fp==NULL){
		printf("no file\n");
		return -2;
	}

	x=0;
	y=0;

	fgets(buf, 1023, fp);
	fgets(buf, 1023, fp);
	fgets(buf, 1023, fp);

	x = y = 0;
	while(fgets(buf, 1023, fp)){
		int col;
		unsigned char R, G, B;
		sscanf(buf, "%4x\n", &col);
		R = col & 0x001F;
		col >>= 5;
		G = col & 0x001F;
		col >>= 5;
		B = col & 0x001F;

		image[y][x*3] = R << 3;
		image[y][x*3+1] = G << 3;
		image[y][x*3+2] = B << 3;
		x++;
		if(x==WIDTH){
			x=0;
			y++;
			if(y==HEIGHT) break;
		}
	}
	fclose(fp);

	printf("%d %d\n", x, y);

	write_png(argv[2], image, WIDTH, HEIGHT);  // PNGファイルを作成します

	system(argv[2]);
	printf("write ok\n");

	for(i=0; i<HEIGHT; i++) free(image[i]);  // 以下2行は2次元配列を解放します
	free(image);

	printf("end\n");

	return 0;
}

C++ core.sfl

	stage read_prg {
		state_name st1,st2;
		first_state st1;
		state st1 if(sram.ack & ^read_chr.do){
			sram.read(0b000 || prg_adrs);
			goto st2;
		}
		state st2 if(sram.ack){
			prg_rdata := sram.rdata<7:0>;
			goto st1;
			finish;
		}
	}

	stage read_chr {
		state_name st1,st2;
		first_state st1;
		state st1 if(sram.ack){
			sram.read(0b00100 || chr_adrs);
			goto st2;
		}
		state st2 if(sram.ack){
			chr_rdata := sram.rdata<7:0>;
			goto st1;
			finish;
		}
	}

C++ sram_ctrl.sfl

top.vhdにて
	SRAM_DQ <= Dout when DEn='0' else (others=>'Z');

// DE1 512KB SRAM IS61LV25616
circuit sram_ctrl
{
	output CEn, OEn, WEn;
	output LBn, UBn, DEn;
	output ADDR<18>;
	input  Din<16>;
	output Dout<16>;

	instrin write(adrs, wdata);
	input adrs<18>, wdata<16>;
	instrin read(adrs);
	output rdata<16>, ack;

	reg_ws oe_reg, we_reg, de_reg;
	reg_wr rdata_reg<16>, wdata_reg<16>, adrs_reg<18>;

	stage_name swrite { task do(adrs_reg, wdata_reg); }
	stage_name sread { task do(adrs_reg); }

	par{
		CEn = 0b0;
		OEn = oe_reg;
		WEn = we_reg;

		LBn = 0b0;
		UBn = 0b0;
		DEn = de_reg;

		ADDR = adrs_reg;
		Dout = wdata_reg;
		rdata = rdata_reg;

		ack = ^(swrite.do | sread.do);
	}

	instruct write par{
		de_reg := 0b0;
		we_reg := 0b0;
		generate swrite.do(adrs, wdata);
	}

	instruct read par{
		oe_reg := 0b0;
		generate sread.do(adrs);
	}

	stage sread {
		par{
			oe_reg := 0b1;
			rdata_reg := Din;
			finish;
		}
	}

	stage swrite {
		state_name st1,st2;
		first_state st1;
		state st1 par{
			we_reg := 0b1;
			goto st2;
		}
		state st2 par{
			de_reg := 0b1;
			goto st1;
			finish;
		}
	}
}

C++ playstation controller

/*
Sony Playstation controller signal decoder
*/
`include "timescale.h"

module scph1080 #(
	parameter DIVIDE_COUNT = 32'd12_000_000 / 32'd500_000
)(
	input reset, clock,
	output reg hid_select, output hid_clock, hid_command,
	input hid_data, hid_ack,
	output reg [15:0] hid_button, hid_debug
);
	parameter SEND1 = 4'd2;
	parameter SEND2 = 4'd4;
	parameter SEND3 = 4'd6;
	parameter SEND4 = 4'd8;
	parameter SEND5 = 4'd10;

	reg [9:0] count;
	wire serialclock = count == 10'd0;
	always @(posedge clock or negedge reset) begin
		if(reset == 1'b0) begin
			count <= 10'd1;
		end else if(count < DIVIDE_COUNT) begin
			count <= count + 10'd1;
		end else begin
			count <= 10'd0;
		end
	end

	reg [4:0] main_sequence, serial_sequence;
	reg transceive, serial_done;
	reg [7:0] indata, outdata;

	assign hid_clock = ~serial_sequence[0];
	assign hid_command = outdata[0];
	//serial transceiver
	always @(negedge reset or posedge clock) begin
		if(reset == 1'b0) begin
			serial_done <= 1'b1;
			serial_sequence <= 5'd0;
		end else if(transceive == 1'b1) begin
			serial_done <= 1'b1;
			serial_sequence <= 5'd0;
		end else if(serialclock && transceive == 1'b0) begin
			case(serial_sequence)
			5'd0: begin //CLK High, CMD set
				case(main_sequence)
				SEND1: outdata <= 8'h01;
				SEND2: outdata <= 8'h42;
				SEND3, SEND4, SEND5: outdata <= 8'h00;
				endcase
				serial_sequence <= serial_sequence + 5'd1;
			end
			5'd1, 5'd3, 5'd5, 5'd7,
			5'd9, 5'd11, 5'd13, 5'd15: begin //CLK Low, DAT get
				indata <= {hid_data, indata[7:1]};
				serial_sequence <= serial_sequence + 5'd1;
			end
			5'd2, 5'd4, 5'd6, 5'd8,
			5'd10, 5'd12, 5'd14: begin
				outdata <= outdata >> 1;
				serial_sequence <= serial_sequence + 5'd1;
			end
			5'd16: serial_done <= 1'b0;
			endcase
		end
	end

	//main sequencer
	reg [5:0] waitcount;
	reg pend_ack;
	always @(posedge clock or negedge reset) begin
		if(reset == 1'b0) begin
			main_sequence <= 4'd0;
			hid_select <= 1'b1;
			transceive <= 1'b1;
			waitcount <= 6'd0;
		end else if(serialclock && waitcount != 6'd0) begin
			waitcount <= waitcount - 6'd1;
			if(waitcount == 6'd1) begin
				main_sequence <= 4'd0;
			end
		end else if(serialclock && waitcount == 6'd0) begin
			case(main_sequence)
			4'd0: begin
				hid_select <= 1'b0;
				main_sequence <= 4'd1;
			end
			4'd1: begin
				transceive <= 1'b0;
				main_sequence <= SEND1;
			end
			SEND1, SEND2, SEND3, SEND4: begin
				pend_ack <= hid_ack;
				if(serial_done == 1'b0 && pend_ack == 1'b0) begin
					transceive <= 1'b1;
					case(main_sequence)
					SEND2: hid_debug[15:8] <= indata;
					SEND3: hid_debug[7:0] <= indata;
					SEND4: hid_button[15:8] <= indata;
					endcase
					main_sequence <= main_sequence + 4'd1;
				end
			end
			SEND1 + 4'd1, SEND2 + 4'd1, SEND3 + 4'd1, SEND4 + 4'd1: begin
				transceive <= 1'b0;
				main_sequence <= main_sequence + 4'd1;
			end
			SEND5: begin //5回目に ack はない
				if(serial_done == 1'b0) begin
					transceive <= 1'b1;
					hid_select <= 1'b1;
					hid_button[7:0] <= indata;
					waitcount <= 6'h1f;
				end
			end
			endcase
		end
	end
endmodule

C++ vga_crtl.sfl

circuit VGA_ctrl
{

	input ht_su<10>, ht_vu<10>, ht_nu<10>, ht_nd<10>, ht_vd<10>, ht_sd<10>;
	input vt_su<10>, vt_vu<10>, vt_nu<10>, vt_nd<10>, vt_vd<10>, vt_sd<10>;
	instrin run;
	instrout nes_hsync;
	instrout nes_vsync;
	instrout dis;
	output hsync, vsync, view_valid, win_valid;

	reg_ws reset;
	reg_wr vsync_count<10>;
	reg_wr h_valid, v_valid;
	reg_wr h_win_valid, v_win_valid;

	stage_name hsync_cnt { task do(); }
	stage_name vsync_cnt { task do(); }

	par{
		if(reset){
			vsync_count := 0b0111111101; // 509
			reset := 0b0;
		}

		view_valid = h_valid & v_valid;
		win_valid = h_win_valid & v_win_valid;
	}

	instruct run par{
		generate hsync_cnt.do();
	}

	// DE1 25 MHz
	stage hsync_cnt {
		reg_wr hsync_reg;
		reg_wr hsync_count<10>;
		reg_wr h_dis_run;
		par{
			hsync = hsync_reg;

			finish;
			any{
				hsync_count==ht_su : par{
					hsync_reg := 0b1;
				}
				hsync_count==ht_vu : par{
					h_valid := 0b1;
				}
				hsync_count==ht_nu : par{
					h_dis_run := 0b1;
				}
				hsync_count==ht_nd : par{
					h_dis_run := 0b0;
				}
				hsync_count==ht_vd : par{
					h_valid := 0b0;
				}
			}
			h_win_valid := h_dis_run;

			if(hsync_count==ht_sd){
				hsync_reg := 0;
				hsync_count := 0;
				generate vsync_cnt.do();
			}
			else{
				hsync_count++;
			}

			if(h_dis_run) dis();
		}
	}

	stage vsync_cnt {
		reg_wr vsync_reg;
		par{
			vsync = vsync_reg;

			finish;
			any{
				vsync_count==vt_su : par{
					vsync_reg := 0b1;
				}
				vsync_count==vt_vu : par{
					v_valid := 0b1;
				}
				vsync_count==vt_nu : par{
					v_win_valid := 0b1;
				}
				vsync_count==vt_nd : par{
					v_win_valid := 0b0;
				}
				vsync_count==vt_vd : par{
					v_valid := 0b0;
				}
			}

			if(vsync_count==vt_sd){
				vsync_reg := 0;
				vsync_count := 0;
				nes_vsync();
			}
			else{
				vsync_count++;
			}

			if(vsync_count<0>){
				nes_hsync();
			}
		}
	}

}

C++ fetch.sfl

// 連続key onのために一旦初期状態に戻す
	stage src_read {
		reg_wr bk_count<3>;
		state_name st_getsl, st_getsh, st_head, st_data;
		first_state st_getsl;
		state st_getsl if((^ready) & f_key & ^read_wait.do){
			// 開始アドレス下位取得
			read(READ_AL, (DIR||0x00) + (0b000000||r_SRCN||f_loop||0b0));
			goto st_getsh;
		}
		state st_getsh any{
			key_on | ^f_key : goto st_getsl;
			else : if(^read_wait.do){
				// 開始アドレス上位取得
				read(READ_AH, (DIR||0x00) + (0b000000||r_SRCN||f_loop||0b1));
				goto st_head;
			}
		}
		state st_head any{
			key_on | ^f_key : goto st_getsl;
			else : if(src_empty & ^read_wait.do){
				// ヘッダ取得
				read(READ_HD, src_AH || src_AL);
				adinc();
				bk_count := 0b000;
				goto st_data;
			}
		}
		state st_data any{
			key_on | ^f_key : goto st_getsl;
			else : if(src_empty & ^read_wait.do){
				// ブロックデータ取得×8
				read(READ_BD, src_AH || src_AL);
				adinc();
				bk_count++;
				if(/&bk_count) any{
					f_end : par{
						goto st_getsl;
						if(^f_loop) finish;
					}
					else : goto st_head;
				}
			}
		}
	}

C++ shift.v

module test;
	wire signed [7:0] data1;
	wire signed [7:0] data2;
    assign data1 = 8'b10000001;
    assign data2 = data1 <<< 2;
endmodule

C++ <<<

module test (dout, co);
	output [7:0] dout;
	output co;

	assign {co, dout} = $signed(8'b10000001) <<< 2;
endmodule

C++ pshid_.nsl

declare pshid {
    output hid_clock, hid_select, hid_command;
    input hid_data, hid_ack;
    output hid_button[16];
}
module pshid {
//#define COUNT (32'd48_000_000 / 32'd250_000)
    reg clock_count[8] = 0xb8;
    reg reg_clock, reg_command;
    reg reg_select = 1;
    reg senddata[8];
    reg reg_button[16];
    proc_name hid_main();
    proc_name serial_access;
    func_self serial_access_go; // 追加

    hid_clock = reg_clock;
    hid_command = reg_command;
    hid_select = reg_select;
    hid_button = reg_button;

    if(clock_count == 0){
        hid_main();
	serial_access();
    }

    any{
        clock_count < 95: clock_count := clock_count + 1;
        else: clock_count := 0;
    }

    proc serial_access{
        reg bitcount[3] = 0;
        reg reg_data[8];
        state_name INIT, SEND_LOW, SEND_HIGH, READ;
	finish;
	state INIT {
		if(serial_access_go) goto SEND_LOW;
	}
        state SEND_LOW{
            //if(clock_count == 0){
                reg_clock := 0;
                reg_command := senddata[0];
                goto SEND_HIGH;
            //}
        }
        state SEND_HIGH{
            //if(clock_count == 0){
                reg_clock := 1;
                reg_data := {hid_data, reg_data[7:1]};
                if(bitcount < 7){
                    senddata := senddata >> 1;
                    bitcount := bitcount + 1;
                }else{
                    bitcount := 0;
                    goto INIT;
                }
            //}
        }
    }

    proc hid_main{
        state_name SEND_01, SEND_42, RECEIVE_5A, GET_SW1, GET_SW2, GET_SW3, IDLE;
        finish;
        state SEND_01{
            reg_select := 0;
            senddata := 8'h01;
            serial_access_go();
            goto SEND_42;
        }
        state SEND_42{
            if(hid_ack == 1'b1){
                senddata := 8'h42;
                serial_access_go(); //return 41
                goto RECEIVE_5A;
            }
        }
        state RECEIVE_5A{
            if(hid_ack == 1'b0){
                senddata := 8'h00;
                serial_access_go(); //return 5a
                goto GET_SW1;
            }
        }
        state GET_SW1{
            if(hid_ack == 1'b0){
                senddata := 8'h00;
                serial_access_go();
                goto GET_SW2;
            }
        }
        state GET_SW2{
            if(hid_ack == 1'b0){
                reg_button := {8'h00, reg_data};
                senddata := 8'h00;
                serial_access_go();
                goto GET_SW3;
            }
        }
        state GET_SW3{
            if(hid_ack == 1'b0){
                reg_button := {reg_button[7:0], reg_data};
                reg_select := 1;
                goto IDLE;
            }
        }
    }

}

C++ pshid

declare pshid {
	output hid_clock, hid_select, hid_command;
	input hid_data, hid_ack;
	output hid_button[16];
}
module pshid {
//#define COUNT (32'd48_000_000 / 32'd250_000)
	reg clock_count[8] = 0xb8;
	reg reg_clock, reg_command;
	reg reg_select = 1;
	reg senddata[8];
	reg reg_button[16];
	proc_name hid_main();
	proc_name serial_access;

	hid_clock = reg_clock;
	hid_command = reg_command;
	hid_select = reg_select;
	hid_button = reg_button;

	if(clock_count == 0){
		hid_main();
	}

	any{
		clock_count < 95: clock_count := clock_count + 1;
		else: clock_count := 0;
	}

	proc serial_access{
		reg bitcount[3] = 0;
		reg reg_data[8];
		state_name SEND_LOW, SEND_HIGH, READ;
		state SEND_LOW{
			//if(clock_count == 0){
				reg_clock := 0;
				reg_command := senddata[0];
				goto SEND_HIGH;
			//}
		}
		state SEND_HIGH{
			//if(clock_count == 0){
				reg_clock := 1;
				reg_data := {hid_data, reg_data[7:1]};
				if(bitcount < 7){
					senddata := senddata >> 1;
					bitcount := bitcount + 1;
					goto SEND_LOW;
				}else{
					bitcount := 0;
					finish();
					goto SEND_LOW;
				}
			//}
		}
	}

	proc hid_main{
		state_name SEND_01, SEND_42, RECEIVE_5A, GET_SW1, GET_SW2, GET_SW3, IDLE;
		finish;
		state SEND_01{
			reg_select := 0;
			senddata := 8'h01;
			serial_access();
			goto SEND_42;
		}
		state SEND_42{
			if(hid_ack == 1'b1){
				senddata := 8'h42;
				serial_access(); //return 41
				goto RECEIVE_5A;
			}
		}
		state RECEIVE_5A{
			if(hid_ack == 1'b0){
				senddata := 8'h00;
				serial_access(); //return 5a
				goto GET_SW1;
			}
		}
		state GET_SW1{
			if(hid_ack == 1'b0){
				senddata := 8'h00;
				serial_access();
				goto GET_SW2;
			}
		}
		state GET_SW2{
			if(hid_ack == 1'b0){
				reg_button := {8'h00, reg_data};
				senddata := 8'h00;
				serial_access();
				goto GET_SW3;
			}
		}
		state GET_SW3{
			if(hid_ack == 1'b0){
				reg_button := {reg_button[7:0], reg_data};
				reg_select := 1;
				goto IDLE;
			}
		}
	}

}
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