#encoding : sjis #Verilog HDLのラベルがないgenerate for文にラベルを付ける require 'fileutils' f = File.open(ARGV[0],"r")
#encoding : sjis #Verilog HDLのラベルがないgenerate for文にラベルを付ける require 'fileutils' f = File.open(ARGV[0],"r+")
// /* Portlist CORDIC_SC cordic (.Clock(Clock),.Reset(Reset),.Start(),.Theta(), .SinOut(),.CosOut(),.Busy(),.End());
//FFT Radix2 DIT 用Index生成module //A-B交互にIndexを出力 /* FFTIndexer_R2 #(.bw_fftp(bw_fftp),.bw_stage(bw_stage)) indexer(.Clock(Clock),Reset(Reset),.Index(),Start(),.Busy(),.End());
module tb; wire signed [7:0] dout; wire signed co; assign {co, dout} = 8'b10000001 <<< 1;