// div_u8.v module div_u8 ( n, d, q, r ); input [7:0] n, d;
/* VISION VJS-372 赤外線レシーバ clk50MHz 受信サンプリング38kHz */
circuit stagepar { instrin run; output vol<3>; reg_wr count<4>;
circuit vga_ctrl { instrin htimming; // 25MHz output h_sync, v_sync; output h_en, v_en;
-- ファイルからRAMへのデータ初期化 procedure ReadFileh( file_name : in string; ram_name : in string; ram_size : in integer;
/* SDRAM Controller 2007/2/14 IS42S16400
component COUNT10 port( RSTn : in std_logic; CLK : in std_logic; TOD : out std_logic_vector(3 downto 0)
// .srm read state st5 if(fat.ack){ fat.fopen(SW<7:0>+0x01); pA := 0b000100 || 0x0000; goto st6;
if(f_direct_color & (bg_mode==0b111) & (m_z_reg==0b001)){ main_col = md7.dir_col; } else{
NMI W $210D 00 0000 W $210D 00 0000 R $0D06 $7F