pgate1さんが投稿したコード一覧

C++ 除算器

// div_u8.v
module div_u8 (
	n, d, q, r
);
	input [7:0] n, d;
	output [7:0] q, r;

	assign q = n / d;
	assign r = n % d;
endmodule

// div_8.sflp
declare div_u8 interface
{
	input n<8>, d<8>;
	output q<8>, r<8>;
}

circuit div_8
{
	input n<8>, d<8>;
	output q<8>, r<8>;
	instrin u(n, d), s(n, d);

	div_u8 div;

	instruct u par{ // unsigned div
		div.n = n;
		div.d = d;
		q = div.q;
		r = div.r;
	}

	instruct s par{ // signed div
		if(n<7>) div.n = -n;
		else div.n = n;
		if(d<7>) div.d = -d;
		else div.d = d;
		if(n<7>@d<7>) q = -div.q;
		else q = div.q;
		if(n<7>) r = -div.r;
		else r = div.r;
	}

}

// div_test.cpp
#include<stdio.h>
#include "Vdiv_8.h"

int main(void)
{
	Vdiv_8 *div = new Vdiv_8;

	int n, d;
	unsigned char q, r;

	for (n = 0; n < 256; n++){
		for (d = 1; d < 256; d++){

			div->n = n;
			div->d = d;

			div->u = 1;
			div->s = 0;
			div->eval();
			printf("H %02X / %02X = %02X . %02X\n", n, d, div->q, div->r);

			q = (unsigned char)n / (unsigned char)d;
			r = (unsigned char)n % (unsigned char)d;
			printf("U %02X / %02X = %02X . %02X\n", n, d, q, r);

			if (div->q != q || div->r != r){
				printf("err\n");
				getchar();
			}

			div->u = 0;
			div->s = 1;
			div->eval();
			printf("H %02X / %02X = %02X . %02X\n", n, d, div->q, div->r);

			q = (signed char)n / (signed char)d;
			r = (signed char)n % (signed char)d;
			printf("S %02X / %02X = %02X . %02X\n", n, d, q, r);

			if (div->q != q || div->r != r){
				printf("err\n");
				getchar();
			}

			printf("\n");
		}
	}

	div->final();
	delete div;

	return 0;
}

C++ 赤外線パッド

/*
 VISION VJS-372 赤外線レシーバ
	clk50MHz 受信サンプリング38kHz
*/

circuit VJS372_receiver
{
	input IRd;
	reg_ws pre0_IRd, pre1_IRd;

	reg_wr div<10>;

	output dout<16>;
	reg_wr dout_reg<16>;

	instrself ir_negedge, ir_posedge;

	stage_name receive_stg { task do(); }

	par{
		// 76kHzでサンプリング
		if(div==657){
			pre0_IRd := IRd;
			generate receive_stg.do();
			div := 0;
		}
		else div++;

		pre1_IRd := pre0_IRd;
		any{
			pre1_IRd & (^pre0_IRd) : ir_negedge();
			(^pre1_IRd) & pre0_IRd : ir_posedge();
		}

		dout = dout_reg;
	}

	stage receive_stg {
		reg_wr head_count<8>, data_count<8>, recv_data<16>;
		reg_wr bit_count<4>, f_push1, f_push2, f_push3;

		state_name idle, headL, headLt, headH, headHt, dataL, dataLt, dataH, dataHt, strtL, strtLt;
		first_state idle;

		par{
			finish;
		}

		state idle par{ // Low待ち
			head_count := 0;
			if(ir_negedge) goto headL;
		}

		// プリアンブル
		state headL par{
			head_count++;
			if(/&head_count) goto idle; // over (error)
			if(ir_posedge) goto headLt;
		}
		state headLt par{
			if((head_count-0x40)<7>==0b0){ // over
				head_count := 0;
				goto headH;
			}
			else goto idle;
		}
		state headH par{
			head_count++;
			if(/&head_count){
				goto idle; // over (error)
			}
			if(ir_negedge) goto headHt;
		}
		state headHt par{
			alt{
				(head_count-0x60)<7>==0b0 : par{ // over (error)
					goto idle;
				}
				(head_count-0x30)<7>==0b0 : par{ // over
					data_count := 0;
					bit_count := 0;
					recv_data := 0x0000;
					goto dataL;
				}
				else : par{ // error
					goto idle;
				}
			}
		}

		state dataL par{
			data_count++;
			f_push1 := 0;
			f_push2 := 0;
			f_push3 := 0;
			if(ir_posedge) goto dataLt;
		}
		state dataLt par{
			alt{
				(0x20-data_count)<7>==0b0 : par{ // under 0x1F
					goto dataH;
				}
				(data_count-0x60)<7>==0b0 : par{ // over (3同時押し) 0x6E
					f_push3 := 1;
					goto dataH;
				}
				(data_count-0x47)<7>==0b0 : par{ // over (2同時押し) 0x4A 0x50
					f_push2 := 1;
					goto dataH;
				}
				else : par{
					f_push1 := 1;
					goto dataH;
				}
			}
			data_count := 0;
		}
		state dataH par{
			data_count++;
			if(/&data_count) goto idle; // over (end frame)
			if(ir_negedge) goto dataHt;
		}
		state dataHt par{
			data_count := 0;
			any{
				bit_count==0 : goto strtL;
				bit_count==14 : par{
					dout_reg := 0b0 || recv_data<15:1>; // キー情報確定
					goto idle;
				}
				else : goto dataL;
			}
			alt{
				// 隣り合うビットのボタンが押されてるとLowが長い
				f_push3 : par{
					recv_data := recv_data<11:0> || 0b1110;
					bit_count += 4;
				}
				// 隣り合うビットのボタンが押されてるとLowが長い
				f_push2 : par{
					recv_data := recv_data<12:0> || 0b110;
					bit_count += 3;
				}
				// ボタンが押されると次のビット情報がパスされる
				f_push1 : par{
					recv_data := recv_data<13:0> || 0b10;
					bit_count += 2;
				}
				else : par{
					recv_data := recv_data<14:0> || 0b0;
					bit_count++;
				}
			}
		}

		// Startだけ長さが違う
		state strtL par{
			data_count++;
			f_push1 := 0;
			f_push2 := 0;
			f_push3 := 0;
			if(ir_posedge) goto strtLt;
		}
		state strtLt par{
			alt{
				(0x06-data_count)<7>==0b0 : par{ // under (error)
					goto idle;
				}
				(0x33-data_count)<7>==0b0 : par{ // under ok 0x28
					goto dataH;
				}
				(data_count-0x65)<7>==0b0 : par{ // over (同時押し) 0x69
					f_push2 := 1;
					goto dataH;
				}
				else : par{
					f_push1 := 1;
					goto dataH;
				}
			}
			data_count := 0;
		}

	}

}

C++ stage内でのoutput出力

circuit stagepar
{
	instrin run;
	output vol<3>;
	reg_wr count<4>;

	stage_name run_stg { task do(); }

	instruct run generate run_stg.do();

	stage run_stg {
		par{
			finish;
			count := count + 1;

			// この記述は常に接続
		//	vol = count<2:0>;
/*
verilog
   assign  vol = (count[2:0]);
*/

			// この記述だとrun_stgトリガ時のみ接続される
			any{
				count<3> : vol = count<2:0>;
				else     : vol = 0b111;
			}
/*
verilog
   assign  vol = ((_net_4)?3'b111:3'b0)|
    ((_net_3)?(count[2:0]):3'b0);
   assign  _net_2 = (count[3]);
   assign  _net_3 = (_stage_run_stg&_net_2);
   assign  _net_4 = (_stage_run_stg&(~_net_2));
*/
		}
	}
/*
VHDLに変換したときのことを考えてこうなっている?
*/

}

TEXT VGAコントローラ

circuit vga_ctrl
{
	instrin htimming; // 25MHz
	output h_sync, v_sync;
	output h_en, v_en;
	output h_count<10>, v_count<10>;

	input iR<4>, iG<4>, iB<4>;
	output oR<4>, oG<4>, oB<4>;

	reg_wr h_tim<10>, v_tim<10>;
	reg_ws h_sync_reg, v_sync_reg;
	reg_wr h_en_reg, v_en_reg;

	instrself vtimming;

	par{
		h_sync = h_sync_reg;
		v_sync = v_sync_reg;

		h_en = h_en_reg;
		v_en = v_en_reg;

		h_count = h_tim - (96+48+1);
		v_count = v_tim - (2+33+1);

		if(h_en & v_en){
			oR = iR; oG = iG; oB = iB;
		}
		else{
			oR = 0; oG = 0; oB = 0;
		}
	}

	instruct htimming par{

		any{
			h_tim==0  : h_sync_reg := 0;
			h_tim==96 : par{
				h_sync_reg := 1;
				vtimming();
			}
			h_tim==(96+48)     : h_en_reg := 1;
			h_tim==(96+48+640) : h_en_reg := 0;
		}

		if(h_tim==(800-1)) h_tim := 0;
		else h_tim++;
	}

	instruct vtimming par{

		any{
			v_tim==0 : v_sync_reg := 0;
			v_tim==2 : v_sync_reg := 1;
			v_tim==(2+33)     : v_en_reg := 1;
			v_tim==(2+33+480) : v_en_reg := 0;
		}

		if(v_tim==(525-1)) v_tim := 0;
		else v_tim++;
	}
}

TEXT ModelSimでVHDLのRAM初期化

-- ファイルからRAMへのデータ初期化
procedure ReadFileh(
	file_name : in string;
	ram_name : in string;
	ram_size : in integer;
	ram_width : in integer) is
file infile : TEXT open read_mode is file_name;
variable l : line;
variable data : std_logic_vector(ram_width-1 downto 0);
begin
	for I in 0 to ram_size-1 loop
		readline(infile, l);
		hread(l, data);
		signal_force(ram_name & "(" & str(I) & ")", str(data), 0 ns, deposit, open, 0);
	end loop;
end;

-- 使い方
	ReadFileh("cgram.dat", "/pu/ppu1/main_cgram/ram0/cells", 256, 16);

TEXT sdram_ctrl.sflp

/*
	SDRAM Controller 2007/2/14

	IS42S16400
		1M Words x 16 bits x 4 Banks (64Mbit)

	clock 50 MHz
		bank<2> adrs<20> data<16>

	QuartusII 7.2 177LC 125DLR
*/

circuit sdram_ctrl
{
	output CSn, RASn, CASn, WEn;
	output LDM, HDM;
	output DEn; // Write data output enable
	output BA<2>, A<12>;
	input Din<16>;
	output Dout<16>;

	instrin write(adrs, wdata);
	input wdata<16>, adrs<22>;
	instrin read(adrs);
	output rdata<16>, ack;

	output err;
	reg_wr err_reg;

	reg_wr BA_reg<2>;
	reg_ws A_reg<12>;
//	reg_ws LDM_reg, HDM_reg;
	reg_ws RASn_reg, CASn_reg, WEn_reg, DEn_reg;

	reg_ws reset;
	reg_wr adrs_reg<22>, rdata_reg<16>, wdata_reg<16>;

	instrself com_NOP, com_PRE, com_REF, com_MRS, com_ACT, com_WRITE, com_READ;

	stage_name init { task do(); }
	stage_name refresh { task do(); }
	stage_name refresh_cnt { task do(); }
	stage_name swrite { task do(adrs_reg, wdata_reg); }
	stage_name sread { task do(adrs_reg); }

	par{
		if(reset){
			reset := 0b0;
			generate init.do();
		}

		ack = ^(init.do | sread.do | swrite.do);

		CSn = 0b0;
		LDM = 0b0; // LDM_reg;
		HDM = 0b0; // HDM_reg;
		RASn = RASn_reg;
		CASn = CASn_reg;
		WEn = WEn_reg;
		DEn = DEn_reg;
		BA = BA_reg;
		A = A_reg;

		Dout = wdata_reg;

		rdata = rdata_reg;

		// for debug
		any{
			init.do & (sread.do | swrite.do) : err_reg := 0b1;
			sread.do & swrite.do : err_reg := 0b1;
			(sread.do & read) | (swrite.do & write) : err_reg := 0b1;
		}
		err = err_reg;
	}

	instruct read par{
		generate sread.do(adrs);
	}

	instruct write par{
		generate swrite.do(adrs, wdata);
	}

	instruct com_NOP par{
		RASn_reg := 0b1;
		CASn_reg := 0b1;
		WEn_reg  := 0b1;
	}

	// Trp 20 ns
	instruct com_PRE par{
		RASn_reg := 0b0;
		CASn_reg := 0b1;
		WEn_reg  := 0b0;
	}

	// Trc 70 ns
	instruct com_REF par{
		RASn_reg := 0b0;
		CASn_reg := 0b0;
		WEn_reg  := 0b1;
	}

	// Trc 10 ns
	instruct com_MRS par{
		RASn_reg := 0b0;
		CASn_reg := 0b0;
		WEn_reg  := 0b0;
	}

	// Trcd 20 ns
	instruct com_ACT par{
		RASn_reg := 0b0;
		CASn_reg := 0b1;
		WEn_reg  := 0b1;
	}

	instruct com_WRITE par{
		RASn_reg := 0b1;
		CASn_reg := 0b0;
		WEn_reg  := 0b0;
	}

	instruct com_READ par{
		RASn_reg := 0b1;
		CASn_reg := 0b0;
		WEn_reg  := 0b1;
	}

	stage init {
		reg_wr init_count<16>, count<6>; // use <14>
		state_name st_PON,st_PALL,st_wPALL1,st_wPALL2,st_REF,st_wREF,st_MRS,st_wMRS;
		first_state st_PON;
		state st_PON par{
			com_NOP();
			init_count++;
			if(init_count==0x2710) goto st_PALL; // 200 us
		}
		state st_PALL par{
			com_PRE();
			A_reg := 0b010000000000; // All banks
			goto st_wPALL1;
		}
		state st_wPALL1 par{
			com_NOP();
			goto st_wPALL2;
		}
		state st_wPALL2 par{
			count++;
			if(/&count) goto st_REF;
		}
		state st_REF par{
			count++;
			if(count<2:0>==0b000) com_REF();
			else com_NOP();
			if(/&count) goto st_wREF;
		}
		state st_wREF par{
			goto st_MRS;
		}
		state st_MRS par{
			com_MRS();
			BA_reg := 0b00;
			A_reg := 0b00000 || 0b010 || 0b0000; // CAS 2 Burst 1
		//	LDM_reg := 0b0;
		//	HDM_reg := 0b0;
			goto st_wMRS;
		}
		state st_wMRS par{
			com_NOP(); // 4回以上
			count++;
			if(count<3>) relay refresh_cnt.do();
		}
	}

// 3 clk
	stage swrite {
		state_name st_ACT, st_WRITEA, st_w1;
		first_state st_ACT;
		state st_ACT if(^refresh.do){
			com_ACT();
			BA_reg := adrs_reg<21:20>;
			A_reg := adrs_reg<19:8>;
			DEn_reg := 0b0;
			goto st_WRITEA;
		}
		state st_WRITEA par{
			com_WRITE();
			A_reg := 0b0100 || adrs_reg<7:0>;
			goto st_w1;
		}
		state st_w1 par{
			com_NOP();
			DEn_reg := 0b1;
			goto st_ACT;
			finish;
		}
	}

// 5 clk
	stage sread {
		state_name st_ACT,st_READA,st_w0,st_w1,st_w2;
		first_state st_ACT;
		state st_ACT if(^refresh.do){
			com_ACT();
			BA_reg := adrs_reg<21:20>;
			A_reg := adrs_reg<19:8>;
			goto st_READA;
		}
		state st_READA par{
			com_READ();
			A_reg := 0b0100 || adrs_reg<7:0>;
			goto st_w0;
		}
		state st_w0 par{
			com_NOP();
			goto st_w1;
		}
		state st_w1 par{
			goto st_w2; // オートプリチャージ
		}
		state st_w2 par{ // CL 2
			rdata_reg := Din;
			goto st_ACT;
			finish;
		}
	}

	stage refresh_cnt {
		reg_wr refresh_time<7>;
		reg_wr notused;
		state_name st1,st2;
		first_state st1;
		if(notused) finish;
		state st1 if(^refresh.do){
			refresh_time++;
			if(/&refresh_time) goto st2;
		}
		state st2 if(^(sread.do | swrite.do)){
			generate refresh.do();
			goto st1;
		}
	}

// 3 clk
// read と refresh が同時に起動しても refresh を優先
	stage refresh {
		reg_wr refresh_A<14>;
		state_name st_ACT, st_PRE, st_wPRE;
		first_state st_ACT;
		state st_ACT par{
			com_ACT();
			BA_reg := refresh_A<1:0>;
			A_reg := refresh_A<13:2>;
			goto st_PRE;
		}
		state st_PRE par{
			com_PRE();
			A_reg := 0b010000000000;
			refresh_A++;
			goto st_wPRE;
		}
		state st_wPRE par{
			com_NOP();
			goto st_ACT;
			finish;
		}
	}

}

TEXT VHDLモジュール接続

  component COUNT10
    port(
      RSTn : in  std_logic;
      CLK  : in  std_logic;
      TOD  : out std_logic_vector(3 downto 0)
    );
  end component;

中略

  CNT10 : COUNT10
    port map(
      RSTn => RSTn,
      CLK  => DCLK,
--    TOD => CBIT,
      TOD(0)  => CBIT(0),
      TOD(1)  => CBIT(1),
      TOD(2)  => CBIT(2),
      TOD(3)  => CBIT(3)
    );

TEXT .srm読み込み

		// .srm read
		state st5 if(fat.ack){
			fat.fopen(SW<7:0>+0x01);
			pA := 0b000100 || 0x0000;
			goto st6;
		}
		state st6 if(fat.ack){
			fat.read();
			goto st7;
		}
		state st7 if(fat.ack & sdram.ack){
			sdram.write(pA, 0x00 || fat.fdata);
			pA++;
			fat.read();
			if(fat.eof) finish;
		}

TEXT DirectColorMode

		if(f_direct_color & (bg_mode==0b111) & (m_z_reg==0b001)){
			main_col = md7.dir_col;
		}
		else{
			main_col = main_cgram.D_out;
		}

TEXT 65C816

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