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TEXT Verilog code for fixed-point 16-bit 4-tap FIR filter module (state machine version)

// Fixed-point 16 bit 4-tap FIR filter module [state machine version] -----------------------
module FIRfilterS (
  input wire[15:0] indata,
  input wire update,
  input wire clk,
  output wire [15:0] outdata
  );
  parameter NTAPS = 4;
  wire signed [15:0] coef[NTAPS-1:0];
  reg  signed [15:0] buff[NTAPS-1:0];
  reg  signed [15:0] outreg,mul_in1,mul_in2;
  wire signed [31:0] mul_out;
  reg  signed [31:0] addreg;
  integer statecnt,rptr,wptr;
  reg inprocess;
  assign outdata = outreg;

  // coefficients --------------- change here
  assign coef[0] = 16'h2000;
  assign coef[1] = 16'h2000;
  assign coef[2] = 16'h2000;
  assign coef[3] = 16'h2000;
  // ------------------------------

  // initital register settings
  initial begin
    rptr <= 0;
    wptr <= 0;
    inprocess <= 0;
    statecnt <= NTAPS*4+1;
  end
  // mulitplication module
  multiplier mul(.clk(clk),.a(mul_in1),.b(mul_in2),.p(mul_out));
    // Optimized 'black-box' module : p = a * b
    //    input clk
    //    input [15:0] a
    //    input [15:0] b
    //    output [31:0] p

  // internal calculations
  always @(posedge clk) begin
    // inpute detection
    if(update==1 && inprocess==0) begin
      buff[wptr] <= indata;
      statecnt <= 0;
      rptr <= wptr;
      addreg <= 0;
      inprocess <= 1;
    end
    // processing state machine
    if(statecnt<NTAPS*4) begin
      if(statecnt%4==0) begin // input data to multiplier
        mul_in1 <= buff[rptr];
        mul_in2 <= coef[statecnt>>4];
      end
      if(statecnt%4==3) begin // get data from multiplier and accumulate
        addreg <= addreg + mul_out;
        rptr <= (rptr+NTAPS-1)%NTAPS;
      end
      statecnt <= statecnt+1;
    end
    if(statecnt==NTAPS*4) begin // output data
      outreg <= addreg>>>15;
      wptr <= (wptr+1)%NTAPS;
      statecnt <= statecnt+1;
    end
    if(statecnt==NTAPS*4+1 && inprocess==1 && update==0) begin
      inprocess <= 0;
    end
  end
endmodule

TEXT Verilog code for 16-bit signed fixed-point N-tap FIR filter module

// Fixed-point 16 bit N-tap FIR filter module -----------------------------
module FIRfilter #(
  parameter NTAPS = 4
  )
  (
  input wire[15:0] indata,
  input wire update,
  input wire inputmode,
  output wire[15:0] outdata
  );
  reg [15:0] coef[NTAPS-1:0];        // coefficients
  wire signed [31:0] mulline[NTAPS-1:0];  // input multiplied with coefficients
  reg  signed [31:0] addline[NTAPS-1:0];  // adder buffer

  // input control
  integer n;
  always @(posedge update) begin
    // coefficients input mode
    if(inputmode==1) begin
      for(n=0;n<NTAPS-1;n=n+1) begin
        coef[NTAPS-n-1] <=coef[NTAPS-n-2];
      end
      coef[0] <= indata;
    end
    // nomal input mode
    else begin
      addline[0] <= mulline[0];
      for(n=0;n<NTAPS-1;n=n+1) begin
        addline[n+1] <= addline[n]+mulline[n+1]; // accumulation
      end
    end
  end
  // multiplication
  genvar i;
  generate
  for(i=0;i<NTAPS;i=i+1) begin : genfil
    multiplier mul(.clk(update),.a(indata),.b(coef[i]),.p(mulline[i]));
    // Optimized 'black-box' module : p = a * b
    //    input clk
    //    input [15:0] a
    //    input [15:0] b
    //    output [31:0] p
  end
  endgenerate
  // output assignment
  assign outdata = addline[NTAPS-1]>>>15;

endmodule

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