VHDLモジュール接続 | Codetter（こーどったー）

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  component COUNT10
    port(
      RSTn : in  std_logic;
      CLK  : in  std_logic;
      TOD  : out std_logic_vector(3 downto 0)
    );
  end component;
中略
  CNT10 : COUNT10
    port map(
      RSTn => RSTn,
      CLK  => DCLK,
--    TOD => CBIT,
      TOD(0)  => CBIT(0),
      TOD(1)  => CBIT(1),
      TOD(2)  => CBIT(2),
      TOD(3)  => CBIT(3)
    );
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