ModelSimでVHDLのRAM初期化 | Codetter（こーどったー）

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-- ファイルからRAMへのデータ初期化
procedure ReadFileh(
    file_name : in string;
    ram_name : in string;
    ram_size : in integer;
    ram_width : in integer) is
file infile : TEXT open read_mode is file_name;
variable l : line;
variable data : std_logic_vector(ram_width-1 downto 0);
begin
    for I in 0 to ram_size-1 loop
        readline(infile, l);
        hread(l, data);
        signal_force(ram_name & "(" & str(I) & ")", str(data), 0 ns, deposit, open, 0);
    end loop;
end;
-- 使い方       
    ReadFileh("cgram.dat", "/pu/ppu1/main_cgram/ram0/cells", 256, 16);
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