Verilog code for 16-bit signed fixed-point N-tap FIR filter module | Codetter（こーどったー）

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// Fixed-point 16 bit N-tap FIR filter module -----------------------------
module FIRfilter #(
  parameter NTAPS = 4
  )
  (
  input wire[15:0] indata,
  input wire update,
  input wire inputmode,
  output wire[15:0] outdata
  );  
  reg [15:0] coef[NTAPS-1:0];        // coefficients
  wire signed [31:0] mulline[NTAPS-1:0];  // input multiplied with coefficients
  reg  signed [31:0] addline[NTAPS-1:0];  // adder buffer
  // input control
  integer n;
  always @(posedge update) begin
    // coefficients input mode
    if(inputmode==1) begin 
      for(n=0;n<NTAPS-1;n=n+1) begin
        coef[NTAPS-n-1] <=coef[NTAPS-n-2];
      end
      coef[0] <= indata;
    end
    // nomal input mode
    else begin
      addline[0] <= mulline[0];
      for(n=0;n<NTAPS-1;n=n+1) begin
        addline[n+1] <= addline[n]+mulline[n+1]; // accumulation
      end
    end
  end
  // multiplication
  genvar i;
  generate 
  for(i=0;i<NTAPS;i=i+1) begin : genfil
    multiplier mul(.clk(update),.a(indata),.b(coef[i]),.p(mulline[i]));
    // Optimized 'black-box' module : p = a * b
    //    input clk
    //    input [15:0] a
    //    input [15:0] b
    //    output [31:0] p
  end
  endgenerate
  // output assignment
  assign outdata = addline[NTAPS-1]>>>15;
endmodule
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