Verilogのtest

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reg [15:0] A;
A = 8'bz010;
1. 0000000000000010
2. zzzzzzzzzzzzz010
3. 1111111111111010
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ModelSim
module test();
reg [15:0] A;
initial begin
A = 8'bz010;
end
endmodule
00000000zzzzz010
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX