module dpram_8x512 ( p_reset, m_clock, radrs, wadrs, din, dout, write, read ); input p_reset, m_clock; input [8:0] radrs, wadrs; input [7:0] din; output [7:0] dout; reg [7:0] dout_reg; input write, read; reg [7:0] cells [0:511]; assign dout = dout_reg; always @(posedge m_clock) begin if(read) dout_reg <= cells[radrs]; end always @(posedge m_clock) begin if(write) cells[wadrs] <= din; end endmodule