%i "ram_8x2k.h" circuit mem_8x2k { input adrs<11>, din<8>; output dout<8>; instrin read(adrs); instrin write(adrs, din); ram_8x2k ram; instrin init; stage_name init_stg { task do(); } par{ dout = ram.dout; } instruct read ram.read(adrs); instruct write ram.write(adrs, din); instruct init init_stg.do(); stage init_stg { reg_wr mem_adrs<11>; par{ ram.write(mem_adrs, 0x00); mem_adrs++; if(/&mem_adrs) finish; } } }