CountLFSR.vhd | Codetter（こーどったー）

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library IEEE;
use IEEE.std_logic_1164.all;
package SUB_PACK is
function m_gen(
    D : integer
)
return std_logic_vector;
end;
package body SUB_PACK is
function m_gen(
    D : integer
)
return std_logic_vector is
variable TMP : std_logic_vector(15 downto 0);
begin
    TMP := X"0001";
    for I in 1 to D loop
        TMP := (TMP(7) xor TMP(0)) & TMP(15 downto 1);
    end loop;
    return TMP;
end;
end SUB_PACK;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.SUB_PACK.all;
entity CountLFSR is
port(
    RST, CLK : in std_logic;
    UP : out std_logic
);
end;
architecture RTL of CountLFSR is
signal count : std_logic_vector(15 downto 0);
signal count_up : std_logic;
begin
    process(RST, CLK) begin
        if(RST='0') then
            count <= X"0001";
        elsif(CLK'event and CLK='1') then
            if(count_up='1') then
                count <= X"0001";
            elsif(count_up='0') then
                count <= (count(7) xor count(0)) & count(15 downto 1);
            end if;
        end if;
    end process;
-- そのままだとよく分からない値を指定する必要がある
--  count_up <= '1' when count=X"8040" else '0';
-- m_gen()使用で20000カウントというのが分かりやすい
    count_up <= '1' when count=m_gen(20000) else '0';
    UP <= count_up;
end RTL;
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