library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TEST_ARY is
port(
nRST : in std_logic;
CLK : in std_logic;
SEL : in std_logic
);
end;
architecture RTL of TEST_ARY is
subtype BIT_ARY_8 is std_logic_vector(7 downto 0);
type BYTE_ARY_CMD1 is array(3 downto 0) of BIT_ARY_8;
signal HEAD_DAT : BYTE_ARY_CMD1;
signal CMD1_DAT : BYTE_ARY_CMD1;
type BYTE_ARY_CMD2 is array(3 downto 0) of BIT_ARY_8;
signal CMD2_DAT : BYTE_ARY_CMD2;
begin
process(nRST, CLK) begin
if(CLK'event and CLK='1') then
case(SEL) is
when '0' =>
-- OK
HEAD_DAT <= CMD1_DAT;
when '1' =>
-- Error Signal "cmd2_dat" is type byte_ary_cmd2; expecting type byte_ary_cmd1.
-- HEAD_DAT <= CMD2_DAT;
-- OK
for i in 0 to 3 loop
HEAD_DAT(i) <= CMD2_DAT(i);
end loop;
when others => null;
end case;
end if;
end process;
end RTL;