TEST_ARY2.vhd | Codetter（こーどったー）

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity TEST_ARY is
port(
	nRST : in std_logic;
	CLK : in std_logic;
	SEL : in std_logic
);
end;
 
architecture RTL of TEST_ARY is
 
	type    BYTE_ARY_CMD1 is array(7 downto 0) of std_logic_vector(7 downto 0);
	signal  HEAD_DAT : BYTE_ARY_CMD1;
	signal  CMD1_DAT : BYTE_ARY_CMD1;
 
	type    BYTE_ARY_CMD2 is array(3 downto 0) of std_logic_vector(7 downto 0);
	signal  CMD2_DAT : BYTE_ARY_CMD2;
 
begin
 
	process(nRST, CLK) begin
		if(CLK'event and CLK='1') then
			case(SEL) is
 
			when '0' =>
				-- OK
				HEAD_DAT <= CMD1_DAT;
 
			when '1' =>
 
-- Error Target type byte_ary_cmd1 in signal assignment is different from expression type byte_ary_cmd2.
			--	HEAD_DAT(3 downto 0) <= CMD2_DAT;
 
				-- OK
				for i in 0 to 3 loop
					HEAD_DAT(i) <= CMD2_DAT(i);
				end loop;
 
			when others => null;
			end case;
		end if;
	end process;
 
end RTL;