declare pshid { output hid_clock, hid_select, hid_command; input hid_data, hid_ack; output hid_button[16]; } module pshid { //#define COUNT (32'd48_000_000 / 32'd250_000) reg clock_count[8] = 0xb8; reg reg_clock, reg_command; reg reg_select = 1; reg senddata[8]; reg reg_button[16]; proc_name hid_main(); proc_name serial_access; func_self serial_access_go; // 追加 hid_clock = reg_clock; hid_command = reg_command; hid_select = reg_select; hid_button = reg_button; if(clock_count == 0){ hid_main(); serial_access(); } any{ clock_count < 95: clock_count := clock_count + 1; else: clock_count := 0; } proc serial_access{ reg bitcount[3] = 0; reg reg_data[8]; state_name INIT, SEND_LOW, SEND_HIGH, READ; finish; state INIT { if(serial_access_go) goto SEND_LOW; } state SEND_LOW{ //if(clock_count == 0){ reg_clock := 0; reg_command := senddata[0]; goto SEND_HIGH; //} } state SEND_HIGH{ //if(clock_count == 0){ reg_clock := 1; reg_data := {hid_data, reg_data[7:1]}; if(bitcount < 7){ senddata := senddata >> 1; bitcount := bitcount + 1; }else{ bitcount := 0; goto INIT; } //} } } proc hid_main{ state_name SEND_01, SEND_42, RECEIVE_5A, GET_SW1, GET_SW2, GET_SW3, IDLE; finish; state SEND_01{ reg_select := 0; senddata := 8'h01; serial_access_go(); goto SEND_42; } state SEND_42{ if(hid_ack == 1'b1){ senddata := 8'h42; serial_access_go(); //return 41 goto RECEIVE_5A; } } state RECEIVE_5A{ if(hid_ack == 1'b0){ senddata := 8'h00; serial_access_go(); //return 5a goto GET_SW1; } } state GET_SW1{ if(hid_ack == 1'b0){ senddata := 8'h00; serial_access_go(); goto GET_SW2; } } state GET_SW2{ if(hid_ack == 1'b0){ reg_button := {8'h00, reg_data}; senddata := 8'h00; serial_access_go(); goto GET_SW3; } } state GET_SW3{ if(hid_ack == 1'b0){ reg_button := {reg_button[7:0], reg_data}; reg_select := 1; goto IDLE; } } } }