sram_ctrl.sfl | Codetter（こーどったー）

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top.vhdにて
    SRAM_DQ <= Dout when DEn='0' else (others=>'Z');
// DE1 512KB SRAM IS61LV25616
circuit sram_ctrl
{
    output CEn, OEn, WEn;
    output LBn, UBn, DEn;
    output ADDR<18>;
    input  Din<16>;
    output Dout<16>;
    instrin write(adrs, wdata);
    input adrs<18>, wdata<16>;
    instrin read(adrs);
    output rdata<16>, ack;
    reg_ws oe_reg, we_reg, de_reg;
    reg_wr rdata_reg<16>, wdata_reg<16>, adrs_reg<18>;
    stage_name swrite { task do(adrs_reg, wdata_reg); }
    stage_name sread { task do(adrs_reg); }
    par{
        CEn = 0b0;
        OEn = oe_reg;
        WEn = we_reg;
        LBn = 0b0;
        UBn = 0b0;
        DEn = de_reg;
        ADDR = adrs_reg;
        Dout = wdata_reg;
        rdata = rdata_reg;
        ack = ^(swrite.do | sread.do);
    }
    instruct write par{
        de_reg := 0b0;
        we_reg := 0b0;
        generate swrite.do(adrs, wdata);
    }
    instruct read par{
        oe_reg := 0b0;
        generate sread.do(adrs);
    }
    stage sread {
        par{
            oe_reg := 0b1;
            rdata_reg := Din;
            finish;
        }
    }
    stage swrite {
        state_name st1,st2;
        first_state st1;
        state st1 par{
            we_reg := 0b1;
            goto st2;
        }
        state st2 par{
            de_reg := 0b1;
            goto st1;
            finish;
        }
    }
}
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