core.sfl

一部抜粋

一部抜粋

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	stage read_prg {
		state_name st1,st2;
		first_state st1;
		state st1 if(sram.ack & ^read_chr.do){
			sram.read(0b000 || prg_adrs);
			goto st2;
		}
		state st2 if(sram.ack){
			prg_rdata := sram.rdata<7:0>;
			goto st1;
			finish;
		}
	}

	stage read_chr {
		state_name st1,st2;
		first_state st1;
		state st1 if(sram.ack){
			sram.read(0b00100 || chr_adrs);
			goto st2;
		}
		state st2 if(sram.ack){
			chr_rdata := sram.rdata<7:0>;
			goto st1;
			finish;
		}
	}